JPS5577068A - Main memory unit - Google Patents

Main memory unit

Info

Publication number
JPS5577068A
JPS5577068A JP14995078A JP14995078A JPS5577068A JP S5577068 A JPS5577068 A JP S5577068A JP 14995078 A JP14995078 A JP 14995078A JP 14995078 A JP14995078 A JP 14995078A JP S5577068 A JPS5577068 A JP S5577068A
Authority
JP
Japan
Prior art keywords
arithmetic unit
main memory
write
unit
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14995078A
Other languages
Japanese (ja)
Inventor
Takayoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14995078A priority Critical patent/JPS5577068A/en
Publication of JPS5577068A publication Critical patent/JPS5577068A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To eliminate an idle state of an arithmetic unit by providing a write- information temporary memory circuit inside of a main memory unit. CONSTITUTION:Write-information temporary memory circuit 21 is provided inside of main memory unit 2, and write information from arithmetic unit 1 is temporarily stored in temporary memory circuit 20 within cycle time. Then, this temporarily- stored write information is written in the cycle time corresponding to the memory element. In this way, the idle time of arithmetic unit 1 is put into several cycles as if continuous write cycles were executed by main memory unit 2 in the cycle time of arithmetic unit 1. Arithmetic unit 1 makes use of this idle time put together so as to eliminate the idle state of arithmetic unit 1.
JP14995078A 1978-12-06 1978-12-06 Main memory unit Pending JPS5577068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14995078A JPS5577068A (en) 1978-12-06 1978-12-06 Main memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14995078A JPS5577068A (en) 1978-12-06 1978-12-06 Main memory unit

Publications (1)

Publication Number Publication Date
JPS5577068A true JPS5577068A (en) 1980-06-10

Family

ID=15486119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14995078A Pending JPS5577068A (en) 1978-12-06 1978-12-06 Main memory unit

Country Status (1)

Country Link
JP (1) JPS5577068A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57135489A (en) * 1981-02-16 1982-08-21 Nippon Telegr & Teleph Corp <Ntt> Storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57135489A (en) * 1981-02-16 1982-08-21 Nippon Telegr & Teleph Corp <Ntt> Storage device
JPS6244352B2 (en) * 1981-02-16 1987-09-19 Nippon Telegraph & Telephone

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