JPS5576442A - Binary coded data adder circuit - Google Patents
Binary coded data adder circuitInfo
- Publication number
- JPS5576442A JPS5576442A JP14794578A JP14794578A JPS5576442A JP S5576442 A JPS5576442 A JP S5576442A JP 14794578 A JP14794578 A JP 14794578A JP 14794578 A JP14794578 A JP 14794578A JP S5576442 A JPS5576442 A JP S5576442A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- plus
- coded data
- binary coded
- rank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To ensure a high-speed and highly expansible operation by delivering only the addition result through the adder circuit, supplying the corresponding binary coded data to be added plus the carry signal sent from the lower-rank digit in order to deliver the presence or absence of the carry signal to the higher-rank digit.
CONSTITUTION: Adder circuits 31W34 plus carry signal generator circuits 35W38 are divided with every 4 bits, and addition data A0WA15 plus B0WB15 are supplied to circuits 31W34 plus 35W38 each. Here circuits 31W34 supply the carry signals from the lower-rank digits plus the corresponding binary coded data to be added to carry out the addition and then to deliver only the addition result. While circuits 35W38 supply the corresponding binary coded data to be added plus the carry signals given from the lower-rank digits to deliver the presence or absence of the carry signal to the higher-rank digit. In this way, the number of the logic gate steps can be reduced as a whole for circuits 31W34, and the propagation length is reduced for the carry signal. As a result, the operation featuring a high speed and high expansibility can be realized.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14794578A JPS5576442A (en) | 1978-12-01 | 1978-12-01 | Binary coded data adder circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14794578A JPS5576442A (en) | 1978-12-01 | 1978-12-01 | Binary coded data adder circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5576442A true JPS5576442A (en) | 1980-06-09 |
Family
ID=15441608
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14794578A Pending JPS5576442A (en) | 1978-12-01 | 1978-12-01 | Binary coded data adder circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5576442A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60179840A (en) * | 1984-02-08 | 1985-09-13 | Yokogawa Hewlett Packard Ltd | Adder |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4951837A (en) * | 1972-09-20 | 1974-05-20 | ||
JPS503549A (en) * | 1973-05-14 | 1975-01-14 |
-
1978
- 1978-12-01 JP JP14794578A patent/JPS5576442A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4951837A (en) * | 1972-09-20 | 1974-05-20 | ||
JPS503549A (en) * | 1973-05-14 | 1975-01-14 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60179840A (en) * | 1984-02-08 | 1985-09-13 | Yokogawa Hewlett Packard Ltd | Adder |
JPH0552530B2 (en) * | 1984-02-08 | 1993-08-05 | Hewlett Packard Co |
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