JPS5575661A - Test unit for integrated circuit - Google Patents

Test unit for integrated circuit

Info

Publication number
JPS5575661A
JPS5575661A JP14890878A JP14890878A JPS5575661A JP S5575661 A JPS5575661 A JP S5575661A JP 14890878 A JP14890878 A JP 14890878A JP 14890878 A JP14890878 A JP 14890878A JP S5575661 A JPS5575661 A JP S5575661A
Authority
JP
Japan
Prior art keywords
pulse
output
integrated circuit
test unit
fed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14890878A
Other languages
Japanese (ja)
Other versions
JPS6138417B2 (en
Inventor
Katsumi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14890878A priority Critical patent/JPS5575661A/en
Publication of JPS5575661A publication Critical patent/JPS5575661A/en
Publication of JPS6138417B2 publication Critical patent/JPS6138417B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To surely enable to compare the pulse pattern and to reduce the test time, by changing the clock pulse fed to IC only when the output pulse of tested IC is present.
CONSTITUTION: The output of the oscillator 21 of the clock generator 11 is frequency-divided 22 to obtain the pulces CP1 and CP2, the pulse CK is fed to the standard IC12 and the sample IC13 via the selector 23, and simultaneously the output pulse position signal generator 25 and the synchronizing signal generator 27 are operated by counting 24 the pulse CK. Thus, the position signals a, b are generated to select the fast pulse CP1 and the slow pulse CP2 and the strobe pulse S is outputted. The output pulses P1 and P2 of IC12 and 13 are compared 14 with pulse S, and output is obtained only when the pulse S is logic 1.
COPYRIGHT: (C)1980,JPO&Japio
JP14890878A 1978-12-01 1978-12-01 Test unit for integrated circuit Granted JPS5575661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14890878A JPS5575661A (en) 1978-12-01 1978-12-01 Test unit for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14890878A JPS5575661A (en) 1978-12-01 1978-12-01 Test unit for integrated circuit

Publications (2)

Publication Number Publication Date
JPS5575661A true JPS5575661A (en) 1980-06-07
JPS6138417B2 JPS6138417B2 (en) 1986-08-29

Family

ID=15463343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14890878A Granted JPS5575661A (en) 1978-12-01 1978-12-01 Test unit for integrated circuit

Country Status (1)

Country Link
JP (1) JPS5575661A (en)

Also Published As

Publication number Publication date
JPS6138417B2 (en) 1986-08-29

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