JPS5574621A - Graph processor - Google Patents

Graph processor

Info

Publication number
JPS5574621A
JPS5574621A JP14651778A JP14651778A JPS5574621A JP S5574621 A JPS5574621 A JP S5574621A JP 14651778 A JP14651778 A JP 14651778A JP 14651778 A JP14651778 A JP 14651778A JP S5574621 A JPS5574621 A JP S5574621A
Authority
JP
Japan
Prior art keywords
input
terminal
closed
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14651778A
Other languages
Japanese (ja)
Inventor
Tokuji Hashiyama
Toshio Ochi
Miyako Nio
Nobunori Matsudaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14651778A priority Critical patent/JPS5574621A/en
Publication of JPS5574621A publication Critical patent/JPS5574621A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the use of combination by arbitrarily selecting the input and output terminals of a plurality without interrupting the program.
CONSTITUTION: The composite terminal control unit 6 having the switch circuits S1, S2 and the interfaces Ia, Ib is provided between the graph processing terminal taking two sets of input terminals Ia, Ib and one set of output terminal 2 as one pair, and the electronic computer 5. Either one of the switches S1 and S2 is closed and the input signal d from the input terminal 1a is fed and displayed at the output terminal 2 in the state of Figure, and it is transferred to the computer 5 as the signal e. When the switch S2 is closed, the input data from the input terminal 1b is similarly processed.
COPYRIGHT: (C)1980,JPO&Japio
JP14651778A 1978-11-29 1978-11-29 Graph processor Pending JPS5574621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14651778A JPS5574621A (en) 1978-11-29 1978-11-29 Graph processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14651778A JPS5574621A (en) 1978-11-29 1978-11-29 Graph processor

Publications (1)

Publication Number Publication Date
JPS5574621A true JPS5574621A (en) 1980-06-05

Family

ID=15409427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14651778A Pending JPS5574621A (en) 1978-11-29 1978-11-29 Graph processor

Country Status (1)

Country Link
JP (1) JPS5574621A (en)

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