JPS5574242A - Logic array - Google Patents

Logic array

Info

Publication number
JPS5574242A
JPS5574242A JP15078779A JP15078779A JPS5574242A JP S5574242 A JPS5574242 A JP S5574242A JP 15078779 A JP15078779 A JP 15078779A JP 15078779 A JP15078779 A JP 15078779A JP S5574242 A JPS5574242 A JP S5574242A
Authority
JP
Japan
Prior art keywords
logic array
logic
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15078779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6119178B2 (enrdf_load_html_response
Inventor
Harii Heren Richiyaado
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Teletype Corp
Original Assignee
Teletype Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teletype Corp filed Critical Teletype Corp
Publication of JPS5574242A publication Critical patent/JPS5574242A/ja
Publication of JPS6119178B2 publication Critical patent/JPS6119178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
JP15078779A 1978-11-29 1979-11-22 Logic array Granted JPS5574242A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/964,568 US4207616A (en) 1978-11-29 1978-11-29 Logic array having improved speed characteristics

Publications (2)

Publication Number Publication Date
JPS5574242A true JPS5574242A (en) 1980-06-04
JPS6119178B2 JPS6119178B2 (enrdf_load_html_response) 1986-05-16

Family

ID=25508711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15078779A Granted JPS5574242A (en) 1978-11-29 1979-11-22 Logic array

Country Status (5)

Country Link
US (1) US4207616A (enrdf_load_html_response)
EP (1) EP0011835B1 (enrdf_load_html_response)
JP (1) JPS5574242A (enrdf_load_html_response)
CA (1) CA1135859A (enrdf_load_html_response)
DE (1) DE2962969D1 (enrdf_load_html_response)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371315A (en) * 1980-09-02 1983-02-01 International Telephone And Telegraph Corporation Pressure booster system with low-flow shut-down control

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55150189A (en) * 1979-05-10 1980-11-21 Nec Corp Memory circuit
US4374384A (en) * 1980-08-28 1983-02-15 Westinghouse Electric Corp. Matrix encoder for resistive sensor arrays
US4395646A (en) * 1980-11-03 1983-07-26 International Business Machines Corp. Logic performing cell for use in array structures
US4536762A (en) * 1982-05-17 1985-08-20 Westinghouse Electric Corp. Matrix encoder for sensor arrays
US4409499A (en) * 1982-06-14 1983-10-11 Standard Microsystems Corporation High-speed merged plane logic function array
US4516040A (en) * 1982-06-14 1985-05-07 Standard Microsystems Corporation High-speed merged plane logic function array
US4583012A (en) * 1983-10-20 1986-04-15 General Instrument Corporation Logical circuit array
EP0189699B1 (en) * 1984-12-26 1992-09-30 STMicroelectronics, Inc. Interdigitated bit line rom
US4571708A (en) * 1984-12-26 1986-02-18 Mostek Corporation CMOS ROM Data select circuit
US4761571A (en) * 1985-12-19 1988-08-02 Honeywell Inc. Memory circuit enchancement to stablize the signal lines with additional capacitance
JP2565213B2 (ja) * 1989-10-27 1996-12-18 ソニー株式会社 読み出し専用メモリ装置
EP0461904A3 (en) * 1990-06-14 1992-09-09 Creative Integrated Systems, Inc. An improved semiconductor read-only vlsi memory
US6339347B1 (en) 2000-03-30 2002-01-15 Intel Corporation Method and apparatus for ratioed logic structure that uses zero or negative threshold voltage

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611437A (en) * 1969-01-16 1971-10-05 Gen Instrument Corp Read-only memory with operative and inoperative data devices located at address stations and with means for controllably charging and discharging appropriate modes of the address stations
US3618050A (en) * 1969-05-07 1971-11-02 Teletype Corp Read-only memory arrays in which a portion of the memory-addressing circuitry is integral to the array
US3613055A (en) * 1969-12-23 1971-10-12 Andrew G Varadi Read-only memory utilizing service column switching techniques
US3747064A (en) * 1971-06-30 1973-07-17 Ibm Fet dynamic logic circuit and layout
US3728696A (en) * 1971-12-23 1973-04-17 North American Rockwell High density read-only memory
US3982138A (en) * 1974-10-09 1976-09-21 Rockwell International Corporation High speed-low cost, clock controlled CMOS logic implementation
GB1560661A (en) * 1975-06-05 1980-02-06 Tokyo Shibaura Electric Co Matrix circuits
US4025799A (en) * 1975-11-06 1977-05-24 Ibm Corporation Decoder structure for a folded logic array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371315A (en) * 1980-09-02 1983-02-01 International Telephone And Telegraph Corporation Pressure booster system with low-flow shut-down control

Also Published As

Publication number Publication date
CA1135859A (en) 1982-11-16
JPS6119178B2 (enrdf_load_html_response) 1986-05-16
EP0011835A1 (en) 1980-06-11
US4207616A (en) 1980-06-10
DE2962969D1 (en) 1982-07-15
EP0011835B1 (en) 1982-05-26

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