JPS5572225A - Improper timing detection circuit - Google Patents

Improper timing detection circuit

Info

Publication number
JPS5572225A
JPS5572225A JP14619778A JP14619778A JPS5572225A JP S5572225 A JPS5572225 A JP S5572225A JP 14619778 A JP14619778 A JP 14619778A JP 14619778 A JP14619778 A JP 14619778A JP S5572225 A JPS5572225 A JP S5572225A
Authority
JP
Japan
Prior art keywords
flip
flops
delay element
circuit
improper timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14619778A
Other languages
Japanese (ja)
Other versions
JPS6141407B2 (en
Inventor
Hiroyuki Izumisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14619778A priority Critical patent/JPS5572225A/en
Publication of JPS5572225A publication Critical patent/JPS5572225A/en
Publication of JPS6141407B2 publication Critical patent/JPS6141407B2/ja
Granted legal-status Critical Current

Links

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To prevent a falut from spreading by immediately detecting the occurrence of improper timing of shorter intervals than preset proper timing, by coupling a delay element with synchronous flip-flops.
CONSTITUTION: This detection circuit consists of synchronous flip-flops 10 and 12, delay element 11 and exclusive OR circuit 13; input data to terminal D of each flip- flop are sampled by timing signal 100 to generate positive and negative outputs at output terminals T and C respectively, delay element 11 generates information on reference time for improper timing detection. Before time (t0), flip-flops are reset and at (t0), and (t1), flip-flops 10 and 12 change with the same polarity, so that circuit 13 will generate no output. At (tE), however, flip-flops 10 and 12 generate outputs of the opposite polarities by the delay element due to a noise and circuit 13 sends out an improper timing detection signal.
COPYRIGHT: (C)1980,JPO&Japio
JP14619778A 1978-11-27 1978-11-27 Improper timing detection circuit Granted JPS5572225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14619778A JPS5572225A (en) 1978-11-27 1978-11-27 Improper timing detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14619778A JPS5572225A (en) 1978-11-27 1978-11-27 Improper timing detection circuit

Publications (2)

Publication Number Publication Date
JPS5572225A true JPS5572225A (en) 1980-05-30
JPS6141407B2 JPS6141407B2 (en) 1986-09-16

Family

ID=15402315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14619778A Granted JPS5572225A (en) 1978-11-27 1978-11-27 Improper timing detection circuit

Country Status (1)

Country Link
JP (1) JPS5572225A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286029A (en) * 1976-01-08 1977-07-16 Sperry Rand Corp Variable frequency clock signal generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286029A (en) * 1976-01-08 1977-07-16 Sperry Rand Corp Variable frequency clock signal generator

Also Published As

Publication number Publication date
JPS6141407B2 (en) 1986-09-16

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