JPS5570170A - Circuit automatic equalizer for analog facsimile - Google Patents

Circuit automatic equalizer for analog facsimile

Info

Publication number
JPS5570170A
JPS5570170A JP14350878A JP14350878A JPS5570170A JP S5570170 A JPS5570170 A JP S5570170A JP 14350878 A JP14350878 A JP 14350878A JP 14350878 A JP14350878 A JP 14350878A JP S5570170 A JPS5570170 A JP S5570170A
Authority
JP
Japan
Prior art keywords
value
supplied
signals
circuit
equalizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14350878A
Other languages
Japanese (ja)
Inventor
Katsuo Murase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP14350878A priority Critical patent/JPS5570170A/en
Publication of JPS5570170A publication Critical patent/JPS5570170A/en
Pending legal-status Critical Current

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Landscapes

  • Facsimile Transmission Control (AREA)

Abstract

PURPOSE: To secure an automatic correction for the transmission distortion in a simple constitution even with the different circuits by installing plural units of equalizers at the reception side to receive the reference signals transmitted and then securing an automatic selective connection for the optimum equalizer featuring the minimum ripple component.
CONSTITUTION: Three units of equalizer E which give correction to the transmission distortion equivalent to one link are connected in series, and the signals b1∼ b4 plus the demodulation signals are supplied to analog switch SW as well as to detection arithmetic circuits A1∼A4. Then gate G1 of circuit A1 is opened for a fixed time to supply demodulation signal b1 to maximum detector P1 for detection of maximum value v, and at the same time, gate G2 is opened to detect steady value w through steady value detector P2. Then these detection value v and w are supplied to division circuit D to calculate the v/w ratio, and this value is supplied to comparison control circuit C to obtain the minimum ratio value. Then the selection signals of signals b1∼b4 corresponding to the minimum value are supplied to switch selection driving circuit S. Circuit S drives switch SW to select the optimum equalizer. As a result, the optimum correction is secured to reproduce a high-contrast reception picture with no ghost.
COPYRIGHT: (C)1980,JPO&Japio
JP14350878A 1978-11-22 1978-11-22 Circuit automatic equalizer for analog facsimile Pending JPS5570170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14350878A JPS5570170A (en) 1978-11-22 1978-11-22 Circuit automatic equalizer for analog facsimile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14350878A JPS5570170A (en) 1978-11-22 1978-11-22 Circuit automatic equalizer for analog facsimile

Publications (1)

Publication Number Publication Date
JPS5570170A true JPS5570170A (en) 1980-05-27

Family

ID=15340353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14350878A Pending JPS5570170A (en) 1978-11-22 1978-11-22 Circuit automatic equalizer for analog facsimile

Country Status (1)

Country Link
JP (1) JPS5570170A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150400A (en) * 1989-11-20 1992-09-22 Ricoh Company, Ltd. Method of controlling a data terminal equipment for equalizing a transmission line characteristic and data terminal equipment using the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4998510A (en) * 1973-01-20 1974-09-18

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4998510A (en) * 1973-01-20 1974-09-18

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150400A (en) * 1989-11-20 1992-09-22 Ricoh Company, Ltd. Method of controlling a data terminal equipment for equalizing a transmission line characteristic and data terminal equipment using the same

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