JPS555698B2 - - Google Patents
Info
- Publication number
- JPS555698B2 JPS555698B2 JP5979672A JP5979672A JPS555698B2 JP S555698 B2 JPS555698 B2 JP S555698B2 JP 5979672 A JP5979672 A JP 5979672A JP 5979672 A JP5979672 A JP 5979672A JP S555698 B2 JPS555698 B2 JP S555698B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5979672A JPS555698B2 (en:Method) | 1972-06-14 | 1972-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5979672A JPS555698B2 (en:Method) | 1972-06-14 | 1972-06-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4919780A JPS4919780A (en:Method) | 1974-02-21 |
| JPS555698B2 true JPS555698B2 (en:Method) | 1980-02-08 |
Family
ID=13123584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5979672A Expired JPS555698B2 (en:Method) | 1972-06-14 | 1972-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS555698B2 (en:Method) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3991305A (en) * | 1974-11-19 | 1976-11-09 | Caudel Edward R | Electronic calculator or digital processor chip with multiple code combinations of display and keyboard scan outputs |
| JPS5291661A (en) * | 1976-01-28 | 1977-08-02 | Toshiba Corp | Semiconductor integrated circuit |
| JPS5295154A (en) * | 1976-02-06 | 1977-08-10 | Nippon Telegr & Teleph Corp <Ntt> | Integrated impedance circuit |
| JPS53121536A (en) * | 1977-03-31 | 1978-10-24 | Toshiba Corp | Semiconductor logic circuit device |
| JPS56126014U (en:Method) * | 1979-07-13 | 1981-09-25 | ||
| JPS58207654A (ja) * | 1982-05-28 | 1983-12-03 | Nippon Telegr & Teleph Corp <Ntt> | 機能モジユ−ルの接続方法およびその接続指定信号生成回路 |
| KR890003691B1 (ko) * | 1986-08-22 | 1989-09-30 | 삼성전자 주식회사 | 블럭 열 리던던씨 회로 |
| JPS63142599A (ja) * | 1986-12-05 | 1988-06-14 | Sony Corp | メモリ装置における不良セルの置換方法 |
| US9692422B2 (en) | 2014-03-17 | 2017-06-27 | Nec Corporation | Programmable logic integrated circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4926270A (en:Method) * | 1972-07-04 | 1974-03-08 |
-
1972
- 1972-06-14 JP JP5979672A patent/JPS555698B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4919780A (en:Method) | 1974-02-21 |