JPS5556727A - Signal converting circuit - Google Patents

Signal converting circuit

Info

Publication number
JPS5556727A
JPS5556727A JP13020978A JP13020978A JPS5556727A JP S5556727 A JPS5556727 A JP S5556727A JP 13020978 A JP13020978 A JP 13020978A JP 13020978 A JP13020978 A JP 13020978A JP S5556727 A JPS5556727 A JP S5556727A
Authority
JP
Japan
Prior art keywords
voltage
clocks
clock
potential
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13020978A
Other languages
Japanese (ja)
Other versions
JPS6412124B2 (en
Inventor
Yuichi Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13020978A priority Critical patent/JPS5556727A/en
Publication of JPS5556727A publication Critical patent/JPS5556727A/en
Publication of JPS6412124B2 publication Critical patent/JPS6412124B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To shorten executive conversion time by varying a voltage by steps from zero to a power voltage by clocks, by applying it to one input terminal of a comparator together with an analog input voltage, and by applying a voltage, rising by a constant potential at fixed intervals of time, to the other input terminal of the comparator.
CONSTITUTION: Control circuit CNT, outputting clocks ϕ1...ϕ3, ϕS, ϕA, and ϕB, consists of two counters N1 and N2. Here, when power voltage VD is denoted by VD, clocks ϕ1...ϕ3, and ϕS are of 0...VDV in amplitude and input voltage V1 is between reference voltage Vref and 0V. Then, applying alternate clocks ϕA and ϕB to FETs T6 and T7 increase a potential at point A, constant potential by constant potential, and when the potential at point A becomes higher than that at point B, the output of comparator CMP is held high. Next, the number of clocks ϕA while clock ϕ3 is low and that of clocks ϕA while clock ϕ1 is low after clock ϕ3 changes from a low level to a high level are counted by counters N1 and N2 to find an unknown voltage, so that the executive conversion time can be shortened.
COPYRIGHT: (C)1980,JPO&Japio
JP13020978A 1978-10-23 1978-10-23 Signal converting circuit Granted JPS5556727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13020978A JPS5556727A (en) 1978-10-23 1978-10-23 Signal converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13020978A JPS5556727A (en) 1978-10-23 1978-10-23 Signal converting circuit

Publications (2)

Publication Number Publication Date
JPS5556727A true JPS5556727A (en) 1980-04-25
JPS6412124B2 JPS6412124B2 (en) 1989-02-28

Family

ID=15028692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13020978A Granted JPS5556727A (en) 1978-10-23 1978-10-23 Signal converting circuit

Country Status (1)

Country Link
JP (1) JPS5556727A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51108561A (en) * 1975-03-19 1976-09-25 Nippon Electric Co Anarogu deijitaruhenkankairo

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51108561A (en) * 1975-03-19 1976-09-25 Nippon Electric Co Anarogu deijitaruhenkankairo

Also Published As

Publication number Publication date
JPS6412124B2 (en) 1989-02-28

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