JPS5555660A - Video signal processing system - Google Patents

Video signal processing system

Info

Publication number
JPS5555660A
JPS5555660A JP12788578A JP12788578A JPS5555660A JP S5555660 A JPS5555660 A JP S5555660A JP 12788578 A JP12788578 A JP 12788578A JP 12788578 A JP12788578 A JP 12788578A JP S5555660 A JPS5555660 A JP S5555660A
Authority
JP
Japan
Prior art keywords
video signal
scanning
memory
written
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12788578A
Other languages
Japanese (ja)
Inventor
Nobuhiro Ito
Yuichi Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Iwatsu Electric Co Ltd
Original Assignee
Iwatsu Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iwatsu Electric Co Ltd filed Critical Iwatsu Electric Co Ltd
Priority to JP12788578A priority Critical patent/JPS5555660A/en
Publication of JPS5555660A publication Critical patent/JPS5555660A/en
Pending legal-status Critical Current

Links

Landscapes

  • Editing Of Facsimile Originals (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Facsimile Scanning Arrangements (AREA)

Abstract

PURPOSE: To obtain higher horizontal resolution, by scanning the original surface without exception and constituting desired video signal through the operation of a plurality of fine video elements scanned.
CONSTITUTION: The information on original is formed on the image sensor 4 via optical system. The sensor 4 driven with the sensor drive unit 11 repeats scanning, for example, ten times during one period of the main scanning. In case of the fifth scanning, the video signal from the video signal amplifying circuit 12 is written in the memory 8 with shaped binary signal in level by the video signal processing circuit 10. Further, the video signal is read in at the 10th scanning, to constitute the binary signal with level shaped, the video signal written in case of fifth scanning is read out from the memory 8, the video signals are compared, and if there is black point in either one, the video signal of dot is made black to write in it in the memory 8. On the other hand, the video signal corresponding to the pre-main scanning is written in the memory 9 during the main scanning period, and the content is outputted with speed conversion. Thus, the memories 8 and 9 perform write-in and readout operation alternately with the memory selection circuit 13 every one scanning.
COPYRIGHT: (C)1980,JPO&Japio
JP12788578A 1978-10-19 1978-10-19 Video signal processing system Pending JPS5555660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12788578A JPS5555660A (en) 1978-10-19 1978-10-19 Video signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12788578A JPS5555660A (en) 1978-10-19 1978-10-19 Video signal processing system

Publications (1)

Publication Number Publication Date
JPS5555660A true JPS5555660A (en) 1980-04-23

Family

ID=14971051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12788578A Pending JPS5555660A (en) 1978-10-19 1978-10-19 Video signal processing system

Country Status (1)

Country Link
JP (1) JPS5555660A (en)

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