JPS5551392A - Time counter - Google Patents

Time counter

Info

Publication number
JPS5551392A
JPS5551392A JP12584278A JP12584278A JPS5551392A JP S5551392 A JPS5551392 A JP S5551392A JP 12584278 A JP12584278 A JP 12584278A JP 12584278 A JP12584278 A JP 12584278A JP S5551392 A JPS5551392 A JP S5551392A
Authority
JP
Japan
Prior art keywords
signal
gate
supplied
circuit
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12584278A
Other languages
Japanese (ja)
Inventor
Kazuo Tsugawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12584278A priority Critical patent/JPS5551392A/en
Publication of JPS5551392A publication Critical patent/JPS5551392A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To stabilize the gate operation for the measurement of the operation time of the breaker or the like by inserting the insulating circuit to one side of the plural units of input signal system, thus ensuring an accurate measurement of the time error even though some potential difference exists between the input signals.
CONSTITUTION: When start input signal (b) is applied to signal lines 31 and 32, signal (b) is supplied to insulating circuit 9 after rectification 4. And the signal drawn out via the photo coupling circuit turns on gate circuit 7. Thus clock signal (a) obtained by dividing 2 the output of reference oscillator 1 is supplied to counter 8 via gate 7. Then with application of stop signal (c) to signal lines 51 and 52, this signal is then supplied to gate 7 after rectification 6 to close gate 7. Thus the time difference between signals (b) and (c) is measured via the count value of counter 8.
COPYRIGHT: (C)1980,JPO&Japio
JP12584278A 1978-10-12 1978-10-12 Time counter Pending JPS5551392A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12584278A JPS5551392A (en) 1978-10-12 1978-10-12 Time counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12584278A JPS5551392A (en) 1978-10-12 1978-10-12 Time counter

Publications (1)

Publication Number Publication Date
JPS5551392A true JPS5551392A (en) 1980-04-15

Family

ID=14920287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12584278A Pending JPS5551392A (en) 1978-10-12 1978-10-12 Time counter

Country Status (1)

Country Link
JP (1) JPS5551392A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194965A (en) * 1985-02-22 1986-08-29 Nippon Denki Syst Kensetsu Kk Telephone voice recording system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61194965A (en) * 1985-02-22 1986-08-29 Nippon Denki Syst Kensetsu Kk Telephone voice recording system

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