JPS5548816A - Peak level display circuit for signal - Google Patents

Peak level display circuit for signal

Info

Publication number
JPS5548816A
JPS5548816A JP12335978A JP12335978A JPS5548816A JP S5548816 A JPS5548816 A JP S5548816A JP 12335978 A JP12335978 A JP 12335978A JP 12335978 A JP12335978 A JP 12335978A JP S5548816 A JPS5548816 A JP S5548816A
Authority
JP
Japan
Prior art keywords
signal
circuit
peak value
input signal
maximum peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12335978A
Other languages
Japanese (ja)
Other versions
JPS6110904B2 (en
Inventor
Chiyuuichi Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP12335978A priority Critical patent/JPS5548816A/en
Publication of JPS5548816A publication Critical patent/JPS5548816A/en
Publication of JPS6110904B2 publication Critical patent/JPS6110904B2/ja
Granted legal-status Critical Current

Links

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE: To enable to correctly grasp the signal having rapid change in the peak value, by displaying the maximum peak value up to the immediately before the signal as well as the peak value of the input signal.
CONSTITUTION: The peak value of audio signal amplifier 1 is detected 2 and it is tentatively ketp at the recovery circuit 3. On the other hand the maximum peak value of signal in the circuit 3 is stored in the circuit 4. Further, if the peak value of input signal is greater than the signal value stored in the memory circuit 2, the output of the reset timing detection circuit 6 operates the reset circuit 5 to keep the memory state of the circuit 4. If the input signal is smaller, the input signal is fed to the display 13 via the switch 8 and the signal in the circuit 4 is via the switch 9. In this case, the amount of passage of the switches 8 and 9 is controlled to display brightly for the input signal and darkly for the maximum peak valve. Thus, the maximum peak value of the input signal can easily be known.
COPYRIGHT: (C)1980,JPO&Japio
JP12335978A 1978-10-03 1978-10-03 Peak level display circuit for signal Granted JPS5548816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12335978A JPS5548816A (en) 1978-10-03 1978-10-03 Peak level display circuit for signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12335978A JPS5548816A (en) 1978-10-03 1978-10-03 Peak level display circuit for signal

Publications (2)

Publication Number Publication Date
JPS5548816A true JPS5548816A (en) 1980-04-08
JPS6110904B2 JPS6110904B2 (en) 1986-03-31

Family

ID=14858620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12335978A Granted JPS5548816A (en) 1978-10-03 1978-10-03 Peak level display circuit for signal

Country Status (1)

Country Link
JP (1) JPS5548816A (en)

Also Published As

Publication number Publication date
JPS6110904B2 (en) 1986-03-31

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