JPS5547772A - Vertical deflection circuit for television receiver - Google Patents

Vertical deflection circuit for television receiver

Info

Publication number
JPS5547772A
JPS5547772A JP12076378A JP12076378A JPS5547772A JP S5547772 A JPS5547772 A JP S5547772A JP 12076378 A JP12076378 A JP 12076378A JP 12076378 A JP12076378 A JP 12076378A JP S5547772 A JPS5547772 A JP S5547772A
Authority
JP
Japan
Prior art keywords
circuit
output
power supply
scanning
vertical deflection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12076378A
Other languages
Japanese (ja)
Inventor
Yasunari Arafune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12076378A priority Critical patent/JPS5547772A/en
Publication of JPS5547772A publication Critical patent/JPS5547772A/en
Pending legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To establish the vertical deflection circuit in low power consumption, by turning on and off the pump up power supply and scanning power supply alternately during scanning and blanking period. CONSTITUTION:The output of the vertical oscillation circuit 11 is fed to the vertical deflection coil 14 via the saw tooth wave generation circuit 12, and vertical amplifying output circuit 13. The comparator 17 compares the output voltage of the output circuit 13 with the scanning power supply Vcc, and when the voltage at the input terminlas A, B is B>=A, an output is made. The logical sum circuit 22 receives the output of the oscillation circuit 11 and comparator 17 to control the switch circuit 21. As a result, during the scanning period, the switch 21 is opened and the scanning power supply Vcc is given to the output circuit 13 via the diode 19. During blanking period, the switch 21 is closed and the pump up power supply, Vcc<Vr, is given to the output circuit 13. In this case, the diode 19 is made to cut-off state.
JP12076378A 1978-09-30 1978-09-30 Vertical deflection circuit for television receiver Pending JPS5547772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12076378A JPS5547772A (en) 1978-09-30 1978-09-30 Vertical deflection circuit for television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12076378A JPS5547772A (en) 1978-09-30 1978-09-30 Vertical deflection circuit for television receiver

Publications (1)

Publication Number Publication Date
JPS5547772A true JPS5547772A (en) 1980-04-04

Family

ID=14794382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12076378A Pending JPS5547772A (en) 1978-09-30 1978-09-30 Vertical deflection circuit for television receiver

Country Status (1)

Country Link
JP (1) JPS5547772A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63100893A (en) * 1986-10-17 1988-05-02 Hitachi Ltd Convergence circuit for display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63100893A (en) * 1986-10-17 1988-05-02 Hitachi Ltd Convergence circuit for display device

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