JPS5546605A - Facsimile packet multiplier - Google Patents

Facsimile packet multiplier

Info

Publication number
JPS5546605A
JPS5546605A JP11861978A JP11861978A JPS5546605A JP S5546605 A JPS5546605 A JP S5546605A JP 11861978 A JP11861978 A JP 11861978A JP 11861978 A JP11861978 A JP 11861978A JP S5546605 A JPS5546605 A JP S5546605A
Authority
JP
Japan
Prior art keywords
facsimile
terminal
processor
control circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11861978A
Inventor
Takeshi Hyodo
Ryuichi Toki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11861978A priority Critical patent/JPS5546605A/en
Publication of JPS5546605A publication Critical patent/JPS5546605A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems
    • H04L12/56Packet switching systems

Abstract

PURPOSE:To make it possible to incorporate a facsimile-terminal circuit in a packet multiplier without alteration, by connecting a control circuit, which controls facsimile terminals, to the direct memory access bus line of a processor in the packet multiplier. CONSTITUTION:Facsimile terminal control circuit 10 which controls facsimile terminals consists of control circuit 18, a reception part and transmission part. To send out packeted data in processor 2 to facsimile terminal 11, the number of bytes equivalent to the volume of data in each packet is set to transmitting byte counter 12, and an initial address to be sent is to address counter 13. Control circuit 18 stores packeted data in buffer memory 14 and sequentially reads and sends them to terminal 11. To receive them, processor 2 sets fixed values to receiving byte counter 15 and address counter 16 facsimile signal from terminal 11 through reception signal line 20 is stored in buffer memory 17 after series-parallel conversion, and then sent to processor 2 through data bus 3.
JP11861978A 1978-09-28 1978-09-28 Facsimile packet multiplier Pending JPS5546605A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11861978A JPS5546605A (en) 1978-09-28 1978-09-28 Facsimile packet multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11861978A JPS5546605A (en) 1978-09-28 1978-09-28 Facsimile packet multiplier

Publications (1)

Publication Number Publication Date
JPS5546605A true JPS5546605A (en) 1980-04-01

Family

ID=14741016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11861978A Pending JPS5546605A (en) 1978-09-28 1978-09-28 Facsimile packet multiplier

Country Status (1)

Country Link
JP (1) JPS5546605A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151768A (en) * 1982-03-05 1983-09-09 Hitachi Ltd Facsimile controller

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391505A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for facsimile circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391505A (en) * 1977-01-24 1978-08-11 Hitachi Ltd Installation system for facsimile circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151768A (en) * 1982-03-05 1983-09-09 Hitachi Ltd Facsimile controller

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