JPS554111A - Control signal transmission system - Google Patents

Abstract

PURPOSE:To miniaturize a system in addition to the great reduction of the number of wires between a master circuit block and slave block, by transmitting multiplex timing information formed of address signals and control signals, which are superposed upon the timing information in series, from the master block to slave block. CONSTITUTION:In master circuit block 4 including address signal generating circuit 2 and control signal generating circuit 3, clock signal S1 and address sognal S2 to be sent to slave circuit blocks 5a and 5b are expressed by address words composed of flag bits and address bits slave circuit blocks 5a and 5b own by combining; and those address words are multiplied in series to form timing information and control signal S3 is multiplied in series on those series-multiplied address words to obtain composite multiplied signal address/control signal S4, which is transferred to all slave circuit blocks 5a, 5b... through bus line 8 making connections between master circuit block 4 and slave circuit blocks 5a and 5b. Then, decoder circuits 7a, 7b... separate and decode the signal for required control.