JPS5539473A - Simultaneous display television receiver for plural program picture - Google Patents

Simultaneous display television receiver for plural program picture

Info

Publication number
JPS5539473A
JPS5539473A JP11331778A JP11331778A JPS5539473A JP S5539473 A JPS5539473 A JP S5539473A JP 11331778 A JP11331778 A JP 11331778A JP 11331778 A JP11331778 A JP 11331778A JP S5539473 A JPS5539473 A JP S5539473A
Authority
JP
Japan
Prior art keywords
frequency
video signals
integer
fold
screen video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11331778A
Other languages
Japanese (ja)
Inventor
Tomomitsu Azeyanagi
Michio Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11331778A priority Critical patent/JPS5539473A/en
Publication of JPS5539473A publication Critical patent/JPS5539473A/en
Pending legal-status Critical Current

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  • Transforming Electric Information Into Light Information (AREA)

Abstract

PURPOSE: To realize a high-quality and reduced picture without increasing the capacity of the memory circuit by sampling the video signals of the slave screen via the integer-fold frequency of each fixed division frequency of the vertical and horizontal scan frequencies of the slave screen video signals and then writing those sampled video signals.
CONSTITUTION: The master screen video signals which are selected and received through master screen tuner 1 are connected to compound circuit 3 via IF and detection circuit 2 and then compounded with the reduced slave screen video signals to be displayed on CRT5. Then the slave screen video signals are sampled with the integer-fold frequency nfV/2 of 1/2 division frequency of vertical scan frequency fV of the slave screen video signal and also with the integer-fold frequency n'fM/r of 1/r frequency of horizontal scan frequency each, and then these sampled video signals are written into memory circuit 9. While these video signals are then read out with the integer- fold frequency mfV'/2 of 1/2 frequency of vertical scan frequency fV' of the master screen video signals and also with the integer-fold frequency m'fM'/S of 1/S frequency of horizontal scan frequency fH' each, thus driving address circuit 14. As a result, a high-quality and reduced picture can be obtained without increasing the capacity of the memory circuit.
COPYRIGHT: (C)1980,JPO&Japio
JP11331778A 1978-09-14 1978-09-14 Simultaneous display television receiver for plural program picture Pending JPS5539473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11331778A JPS5539473A (en) 1978-09-14 1978-09-14 Simultaneous display television receiver for plural program picture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11331778A JPS5539473A (en) 1978-09-14 1978-09-14 Simultaneous display television receiver for plural program picture

Publications (1)

Publication Number Publication Date
JPS5539473A true JPS5539473A (en) 1980-03-19

Family

ID=14609157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11331778A Pending JPS5539473A (en) 1978-09-14 1978-09-14 Simultaneous display television receiver for plural program picture

Country Status (1)

Country Link
JP (1) JPS5539473A (en)

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