JPS5539072B2 - - Google Patents

Info

Publication number
JPS5539072B2
JPS5539072B2 JP11862272A JP11862272A JPS5539072B2 JP S5539072 B2 JPS5539072 B2 JP S5539072B2 JP 11862272 A JP11862272 A JP 11862272A JP 11862272 A JP11862272 A JP 11862272A JP S5539072 B2 JPS5539072 B2 JP S5539072B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP11862272A
Other versions
JPS4878836A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4878836A publication Critical patent/JPS4878836A/ja
Publication of JPS5539072B2 publication Critical patent/JPS5539072B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP11862272A 1971-12-30 1972-11-28 Expired JPS5539072B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00214364A US3800295A (en) 1971-12-30 1971-12-30 Asynchronously operated memory system

Publications (2)

Publication Number Publication Date
JPS4878836A JPS4878836A (ja) 1973-10-23
JPS5539072B2 true JPS5539072B2 (ja) 1980-10-08

Family

ID=22798792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11862272A Expired JPS5539072B2 (ja) 1971-12-30 1972-11-28

Country Status (7)

Country Link
US (1) US3800295A (ja)
JP (1) JPS5539072B2 (ja)
CA (1) CA975466A (ja)
DE (1) DE2252489A1 (ja)
FR (1) FR2166225B1 (ja)
GB (1) GB1356530A (ja)
IT (1) IT970965B (ja)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2247835C3 (de) * 1972-09-29 1978-10-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Regenerieren der Speicherinhalte von MOS-Speichern und MOS-Speicher zur Durchführung dieses Verfahrens
US4028675A (en) * 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
NL7410610A (nl) * 1973-08-10 1975-02-12 Data General Corp Stelsel voor het verwerken van gegevens.
USRE30331E (en) * 1973-08-10 1980-07-08 Data General Corporation Data processing system having a unique CPU and memory timing relationship and data path configuration
US3986176A (en) * 1975-06-09 1976-10-12 Rca Corporation Charge transfer memories
JPS589510B2 (ja) * 1975-08-08 1983-02-21 三菱電機株式会社 キオクソウチ
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
JPS5255337A (en) * 1975-10-31 1977-05-06 Hitachi Ltd Refresh control system
US4172282A (en) * 1976-10-29 1979-10-23 International Business Machines Corporation Processor controlled memory refresh
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
IT1117301B (it) * 1977-05-25 1986-02-17 Olivetti & Co Spa Calcotore elettronico con dispositivo di rinfresco di una memoria operativa dinamica
JPS588075B2 (ja) * 1977-07-29 1983-02-14 富士通株式会社 メモリ・アレイ・カ−ド
US4238842A (en) * 1978-12-26 1980-12-09 Ibm Corporation LARAM Memory with reordered selection sequence for refresh
JPS55132593A (en) * 1979-04-02 1980-10-15 Fujitsu Ltd Refresh control method for memory unit
FR2474227A1 (fr) * 1980-01-17 1981-07-24 Cii Honeywell Bull Procede de rafraichissement pour banc de memoire a circuit " mos " et sequenceur correspondant
JPS59140694A (ja) * 1983-01-31 1984-08-13 Sharp Corp ダイナミツクｒａｍのリフレツシユ方法
AT389014B (de) * 1983-09-30 1989-10-10 Schoellauf Hannes Ing Zentraleinheit mit speicher
US4701843A (en) * 1985-04-01 1987-10-20 Ncr Corporation Refresh system for a page addressable memory
US5193165A (en) * 1989-12-13 1993-03-09 International Business Machines Corporation Memory card refresh buffer
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5335201A (en) * 1991-04-15 1994-08-02 Micron Technology, Inc. Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs
US5379400A (en) * 1992-08-07 1995-01-03 International Business Machines Corp. Method and system for determining memory refresh rate
US5638529A (en) * 1992-08-24 1997-06-10 Intel Corporation Variable refresh intervals for system devices including setting the refresh interval to zero
US5617551A (en) * 1992-09-18 1997-04-01 New Media Corporation Controller for refreshing a PSRAM using individual automatic refresh cycles
AU6988494A (en) * 1993-05-28 1994-12-20 Rambus Inc. Method and apparatus for implementing refresh in a synchronous dram system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599180A (en) * 1968-11-29 1971-08-10 Gen Instrument Corp Random access read-write memory system having data refreshing capabilities and memory cell therefor
US3665422A (en) * 1970-01-26 1972-05-23 Electronic Arrays Integrated circuit,random access memory
US3705392A (en) * 1971-09-07 1972-12-05 Texas Instruments Inc Mos dynamic memory
US3760379A (en) * 1971-12-29 1973-09-18 Honeywell Inf Systems Apparatus and method for memory refreshment control

Also Published As

Publication number Publication date
CA975466A (en) 1975-09-30
IT970965B (it) 1974-04-20
FR2166225B1 (ja) 1976-08-27
FR2166225A1 (ja) 1973-08-10
US3800295A (en) 1974-03-26
JPS4878836A (ja) 1973-10-23
DE2252489A1 (de) 1973-07-05
GB1356530A (en) 1974-06-12

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