JPS5538823B2 - - Google Patents

Info

Publication number
JPS5538823B2
JPS5538823B2 JP10487871A JP10487871A JPS5538823B2 JP S5538823 B2 JPS5538823 B2 JP S5538823B2 JP 10487871 A JP10487871 A JP 10487871A JP 10487871 A JP10487871 A JP 10487871A JP S5538823 B2 JPS5538823 B2 JP S5538823B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10487871A
Other versions
JPS4869478A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10487871A priority Critical patent/JPS5538823B2/ja
Priority to US00310168A priority patent/US3833429A/en
Publication of JPS4869478A publication Critical patent/JPS4869478A/ja
Publication of JPS5538823B2 publication Critical patent/JPS5538823B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
JP10487871A 1971-12-22 1971-12-22 Expired JPS5538823B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10487871A JPS5538823B2 (ja) 1971-12-22 1971-12-22
US00310168A US3833429A (en) 1971-12-22 1972-11-28 Method of manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10487871A JPS5538823B2 (ja) 1971-12-22 1971-12-22

Publications (2)

Publication Number Publication Date
JPS4869478A JPS4869478A (ja) 1973-09-20
JPS5538823B2 true JPS5538823B2 (ja) 1980-10-07

Family

ID=14392444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10487871A Expired JPS5538823B2 (ja) 1971-12-22 1971-12-22

Country Status (2)

Country Link
US (1) US3833429A (ja)
JP (1) JPS5538823B2 (ja)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3981072A (en) * 1973-05-25 1976-09-21 Trw Inc. Bipolar transistor construction method
FR2282162A1 (fr) * 1974-08-12 1976-03-12 Radiotechnique Compelec Procede de realisation de dispositifs semiconducteurs
JPS51127682A (en) * 1975-04-30 1976-11-06 Fujitsu Ltd Manufacturing process of semiconductor device
USRE30282E (en) * 1976-06-28 1980-05-27 Motorola, Inc. Double master mask process for integrated circuit manufacture
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
US4110126A (en) * 1977-08-31 1978-08-29 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
CA1116309A (en) * 1977-11-30 1982-01-12 David L. Bergeron Structure and process for optimizing the characteristics of i.sup.2l devices
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
JPS6028397B2 (ja) * 1978-10-26 1985-07-04 株式会社東芝 半導体装置の製造方法
JPS56169322A (en) * 1980-05-30 1981-12-26 Fujikura Ltd Selective diffusion of boron into silicon
US4443932A (en) * 1982-01-18 1984-04-24 Motorla, Inc. Self-aligned oxide isolated process and device
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
US4648909A (en) * 1984-11-28 1987-03-10 Fairchild Semiconductor Corporation Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits
US4860085A (en) * 1986-06-06 1989-08-22 American Telephone And Telegraph Company, At&T Bell Laboratories Submicron bipolar transistor with buried silicide region
JPS6393153A (ja) * 1986-10-07 1988-04-23 Toshiba Corp 半導体装置の製造方法
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
US6539526B1 (en) * 1999-12-22 2003-03-25 Texas Instruments Incorporated Method and apparatus for determining capacitances for a device within an integrated circuit
TWI413240B (zh) * 2007-05-07 2013-10-21 Sony Corp A solid-state imaging device, a manufacturing method thereof, and an image pickup device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3479237A (en) * 1966-04-08 1969-11-18 Bell Telephone Labor Inc Etch masks on semiconductor surfaces
US3494809A (en) * 1967-06-05 1970-02-10 Honeywell Inc Semiconductor processing
NL152707B (nl) * 1967-06-08 1977-03-15 Philips Nv Halfgeleiderinrichting bevattende een veldeffecttransistor van het type met geisoleerde poortelektrode en werkwijze ter vervaardiging daarvan.
US3717514A (en) * 1970-10-06 1973-02-20 Motorola Inc Single crystal silicon contact for integrated circuits and method for making same
US3725150A (en) * 1971-10-29 1973-04-03 Motorola Inc Process for making a fine geometry, self-aligned device structure

Also Published As

Publication number Publication date
US3833429A (en) 1974-09-03
JPS4869478A (ja) 1973-09-20

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