JPS5534772A - Wrong address detection mechanism - Google Patents

Wrong address detection mechanism

Info

Publication number
JPS5534772A
JPS5534772A JP10834978A JP10834978A JPS5534772A JP S5534772 A JPS5534772 A JP S5534772A JP 10834978 A JP10834978 A JP 10834978A JP 10834978 A JP10834978 A JP 10834978A JP S5534772 A JPS5534772 A JP S5534772A
Authority
JP
Japan
Prior art keywords
signal
address
instruction
micro
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10834978A
Other languages
Japanese (ja)
Inventor
Koichi Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10834978A priority Critical patent/JPS5534772A/en
Publication of JPS5534772A publication Critical patent/JPS5534772A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To detect the wrong address in the information processing device by forming the circuit which judges if the interrupt inhibition bit in the micro-instruction and the address of the micro-instruction have been subject to adressing.
CONSTITUTION: The address 5 is stored in the register 7 by receiving the micro- instruction address 5 and its receiving signal 6 from the information processing device 1, its contents are stored in the register 8 with the timing T3, these contents are subtracted by the subtraction circuit 9, and in case its result is not "1", "1" is set to INCFF 10 with the timing T2. Subsequently, AND is taken by the AND circuit 12 concerning the output of FF 10 and the output of the interrupt inhibition bit FF 3, and the signal of the mode changeover instruction signal 11, and it is set to the error FF 13 with the timing T3. And in case FF 13 has been set to ON, the error detection signal 14 becomes ON, and this signal is transmitted to the information processing device 1.
COPYRIGHT: (C)1980,JPO&Japio
JP10834978A 1978-09-04 1978-09-04 Wrong address detection mechanism Pending JPS5534772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10834978A JPS5534772A (en) 1978-09-04 1978-09-04 Wrong address detection mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10834978A JPS5534772A (en) 1978-09-04 1978-09-04 Wrong address detection mechanism

Publications (1)

Publication Number Publication Date
JPS5534772A true JPS5534772A (en) 1980-03-11

Family

ID=14482443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10834978A Pending JPS5534772A (en) 1978-09-04 1978-09-04 Wrong address detection mechanism

Country Status (1)

Country Link
JP (1) JPS5534772A (en)

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