JPS5534309A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5534309A
JPS5534309A JP10603878A JP10603878A JPS5534309A JP S5534309 A JPS5534309 A JP S5534309A JP 10603878 A JP10603878 A JP 10603878A JP 10603878 A JP10603878 A JP 10603878A JP S5534309 A JPS5534309 A JP S5534309A
Authority
JP
Japan
Prior art keywords
circuit
memory
row select
matrix
efficiency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10603878A
Other languages
Japanese (ja)
Inventor
Kazunori Ouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10603878A priority Critical patent/JPS5534309A/en
Publication of JPS5534309A publication Critical patent/JPS5534309A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To dispose the row select circuit and the efficiency circuit at the same side as the memory matrix, thereby read out the information of the semiconductor memory device of one element stably and at high speed. CONSTITUTION:All the row select lines 11 are connected to the row select circuit 20 disposed at one side of the memory matrix 14. All the sense amplifiers 15 are connected to the sense amplifier efficiency circuit 22 disposed at the same side of the matrix as that to which the circuit 20 is placed through the latch bus 21. In this way, when the memory 13 is made access most adjacently to the circuit 20, the row select signal and the efficiency signal indicate the abrupt rising and lowering. In the case the memory is made access which is the farthest from the circuit 20, both the signals show gentle rising and lowering properties. Therefore, in either case, the full distribution of charge between the memory cell and the data line is carried out. As a result, the reading out of the information can be performed stably and at high speed.
JP10603878A 1978-08-30 1978-08-30 Semiconductor memory device Pending JPS5534309A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10603878A JPS5534309A (en) 1978-08-30 1978-08-30 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10603878A JPS5534309A (en) 1978-08-30 1978-08-30 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5534309A true JPS5534309A (en) 1980-03-10

Family

ID=14423461

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10603878A Pending JPS5534309A (en) 1978-08-30 1978-08-30 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5534309A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595490A (en) * 1982-07-01 1984-01-12 Mitsubishi Electric Corp Semiconductor memory
JPS6168797A (en) * 1984-09-11 1986-04-09 Nec Corp Dynamic memory circuit
JPS61104395A (en) * 1984-10-22 1986-05-22 Nec Ic Microcomput Syst Ltd Dynamic type semiconductor storage device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595490A (en) * 1982-07-01 1984-01-12 Mitsubishi Electric Corp Semiconductor memory
JPH0424800B2 (en) * 1982-07-01 1992-04-28 Mitsubishi Electric Corp
JPS6168797A (en) * 1984-09-11 1986-04-09 Nec Corp Dynamic memory circuit
JPH0414437B2 (en) * 1984-09-11 1992-03-12 Nippon Electric Co
JPS61104395A (en) * 1984-10-22 1986-05-22 Nec Ic Microcomput Syst Ltd Dynamic type semiconductor storage device
JPH0363156B2 (en) * 1984-10-22 1991-09-30 Nippon Denki Aishii Maikon Shisutemu Kk

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