JPS5530242A - Fm receiver - Google Patents

Fm receiver

Info

Publication number
JPS5530242A
JPS5530242A JP10350278A JP10350278A JPS5530242A JP S5530242 A JPS5530242 A JP S5530242A JP 10350278 A JP10350278 A JP 10350278A JP 10350278 A JP10350278 A JP 10350278A JP S5530242 A JPS5530242 A JP S5530242A
Authority
JP
Japan
Prior art keywords
signal
circuit
supplied
demodulated
intermediate frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10350278A
Other languages
Japanese (ja)
Inventor
Teruo Sato
Naoki Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10350278A priority Critical patent/JPS5530242A/en
Publication of JPS5530242A publication Critical patent/JPS5530242A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a demodulated signal with distortion canceled by providing two FM modulator circuits differing mutually in characteristics and then by correcting the modulated signal of the main demodulator circuit by that of the sub-modulator circuit.
CONSTITUTION: An intermediate frequency signal from intermediate frequency amplifier 2 is supplied to FM demodulator circuit 3 and demodulated signal E1 is also supplied to adder circuit 4. An intermediate frequency signal from amplifier 2 is supplied to FM demodulator circuit 5, whose demodulated signal E2 is supplied to circuit 4 via correction circuit 6 for polarity and level. The output of circuit 4 is supplied to addition-output stereophonic demodulator circuit 7, where right and left stereophonic signals are demodulated and extracted from output terminals 5L and 5R. Circuit 6 selects the level and polarity of signal E2 to cancel ternary distortion α3cos3ωt in signal E1 by signal E2. Difference frequency ΔF is changed and fixed by circuit 5 to cancel secondary distortion α2cos2ωt in signal E1 by signal E2.
COPYRIGHT: (C)1980,JPO&Japio
JP10350278A 1978-08-25 1978-08-25 Fm receiver Pending JPS5530242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10350278A JPS5530242A (en) 1978-08-25 1978-08-25 Fm receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10350278A JPS5530242A (en) 1978-08-25 1978-08-25 Fm receiver

Publications (1)

Publication Number Publication Date
JPS5530242A true JPS5530242A (en) 1980-03-04

Family

ID=14355746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10350278A Pending JPS5530242A (en) 1978-08-25 1978-08-25 Fm receiver

Country Status (1)

Country Link
JP (1) JPS5530242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56156028A (en) * 1980-05-06 1981-12-02 Fujitsu Ltd Carrier detecting circuit
US4878251A (en) * 1985-04-29 1989-10-31 Plessey Overseas Limited Interference signal suppressor for a radio receiver

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56156028A (en) * 1980-05-06 1981-12-02 Fujitsu Ltd Carrier detecting circuit
JPS6234184B2 (en) * 1980-05-06 1987-07-24 Fujitsu Ltd
US4878251A (en) * 1985-04-29 1989-10-31 Plessey Overseas Limited Interference signal suppressor for a radio receiver

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