JPS5527667A - Method of manufacturing insulating substrate for semiconductor element and semiconductor device - Google Patents

Method of manufacturing insulating substrate for semiconductor element and semiconductor device

Info

Publication number
JPS5527667A
JPS5527667A JP10111978A JP10111978A JPS5527667A JP S5527667 A JPS5527667 A JP S5527667A JP 10111978 A JP10111978 A JP 10111978A JP 10111978 A JP10111978 A JP 10111978A JP S5527667 A JPS5527667 A JP S5527667A
Authority
JP
Japan
Prior art keywords
holes
grooves
plural
island regions
center
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10111978A
Other languages
Japanese (ja)
Inventor
Katsunori Ochi
Toshinobu Banjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10111978A priority Critical patent/JPS5527667A/en
Publication of JPS5527667A publication Critical patent/JPS5527667A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

PURPOSE: To enable automation and make mass production easy in an operation to attach semiconductor chips to an insulator substrate having conductive stripes, by forming plural island regions limited by grooves and the first and the second holes on the insulator substrate.
CONSTITUTION: A copper plate is coated on the principal surface 11a of a glass epoxy substrate 11: removing the copper plate selectively by a photoengraving process, conductive stripe groups 2 are formed: further, by forming vertical grooves 12b and horizonral grooves 12a having V-shape cross sections, island regions 15 are formed. Next, plural feed holes 13 and plural locating holes 14 for the automatic wiring of thin metallic wire 5 are formed by a photoetching process. The feed holes 13 are rectangular holes and are provided in such a way that they are parallel to the horizontal grooves 12a and the center of each hole coincides with the center line of a vertical groove 12b, the locating holes 14 are round holes and are provided so that each one of them is located in the center of two adjacent vertical grooves 12b: and they are both provided outside the island regions 15.
COPYRIGHT: (C)1980,JPO&Japio
JP10111978A 1978-08-18 1978-08-18 Method of manufacturing insulating substrate for semiconductor element and semiconductor device Pending JPS5527667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10111978A JPS5527667A (en) 1978-08-18 1978-08-18 Method of manufacturing insulating substrate for semiconductor element and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10111978A JPS5527667A (en) 1978-08-18 1978-08-18 Method of manufacturing insulating substrate for semiconductor element and semiconductor device

Publications (1)

Publication Number Publication Date
JPS5527667A true JPS5527667A (en) 1980-02-27

Family

ID=14292179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10111978A Pending JPS5527667A (en) 1978-08-18 1978-08-18 Method of manufacturing insulating substrate for semiconductor element and semiconductor device

Country Status (1)

Country Link
JP (1) JPS5527667A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61143663A (en) * 1985-11-20 1986-07-01 松下電器産業株式会社 Refrigeration cycle device for air conditioner with refrigerant heater
JP2007276857A (en) * 2006-04-11 2007-10-25 Aaki Kk Board for maintaining shape of folded shirt

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61143663A (en) * 1985-11-20 1986-07-01 松下電器産業株式会社 Refrigeration cycle device for air conditioner with refrigerant heater
JPS6342180B2 (en) * 1985-11-20 1988-08-22 Matsushita Electric Ind Co Ltd
JP2007276857A (en) * 2006-04-11 2007-10-25 Aaki Kk Board for maintaining shape of folded shirt

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