|
JPS5148937A
(en)
*
|
1974-10-25 |
1976-04-27 |
Fujitsu Ltd |
Kiokusochi niokeru junjoseigyohoshiki
|
|
JPS5848146A
(ja)
*
|
1981-09-18 |
1983-03-22 |
Toshiba Corp |
命令先取り方式
|
|
US4477872A
(en)
*
|
1982-01-15 |
1984-10-16 |
International Business Machines Corporation |
Decode history table for conditional branch instructions
|
|
JPS6015745A
(ja)
*
|
1983-07-06 |
1985-01-26 |
Nec Corp |
情報処理装置
|
|
US4578750A
(en)
*
|
1983-08-24 |
1986-03-25 |
Amdahl Corporation |
Code determination using half-adder based operand comparator
|
|
JPH0769818B2
(ja)
*
|
1984-10-31 |
1995-07-31 |
株式会社日立製作所 |
デ−タ処理装置
|
|
US4747046A
(en)
*
|
1985-06-28 |
1988-05-24 |
Hewlett-Packard Company |
Mechanism for comparing two registers and storing the result in a general purpose register without requiring a branch
|
|
JPS62226232A
(ja)
*
|
1986-03-28 |
1987-10-05 |
Toshiba Corp |
分岐先アドレス算出回路
|
|
US4845659A
(en)
*
|
1986-08-15 |
1989-07-04 |
International Business Machines Corporation |
Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations
|
|
US4841476A
(en)
*
|
1986-10-06 |
1989-06-20 |
International Business Machines Corporation |
Extended floating point operations supporting emulation of source instruction execution
|
|
US4967351A
(en)
*
|
1986-10-17 |
1990-10-30 |
Amdahl Corporation |
Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination
|
|
JP2723238B2
(ja)
*
|
1988-01-18 |
1998-03-09 |
株式会社東芝 |
情報処理装置
|
|
JPH023822A
(ja)
*
|
1988-06-21 |
1990-01-09 |
Matsushita Electric Ind Co Ltd |
データ処理装置
|
|
KR0136594B1
(ko)
*
|
1988-09-30 |
1998-10-01 |
미다 가쓰시게 |
단일칩 마이크로 컴퓨터
|
|
DE68927218T2
(de)
*
|
1988-10-18 |
1997-02-06 |
Hewlett Packard Co |
Verfahren und Vorrichtung für Zustandskode in einem Zentralprozessor
|
|
US5099419A
(en)
*
|
1988-11-25 |
1992-03-24 |
Nec Corporation |
Pipeline microcomputer having branch instruction detector and bus controller for producing and carrying branch destination address prior to instruction execution
|
|
CA2016068C
(en)
*
|
1989-05-24 |
2000-04-04 |
Robert W. Horst |
Multiple instruction issue computer architecture
|
|
US5255371A
(en)
*
|
1990-04-02 |
1993-10-19 |
Unisys Corporation |
Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands
|
|
US5872910A
(en)
*
|
1996-12-27 |
1999-02-16 |
Unisys Corporation |
Parity-error injection system for an instruction processor
|
|
EP1236097A4
(en)
|
1999-09-01 |
2006-08-02 |
Intel Corp |
BRANCH COMMAND TO THE PROCESSOR
|
|
US7546444B1
(en)
|
1999-09-01 |
2009-06-09 |
Intel Corporation |
Register set used in multithreaded parallel processor architecture
|
|
US7681018B2
(en)
|
2000-08-31 |
2010-03-16 |
Intel Corporation |
Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
|
|
US7225281B2
(en)
|
2001-08-27 |
2007-05-29 |
Intel Corporation |
Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
|
|
US7216204B2
(en)
|
2001-08-27 |
2007-05-08 |
Intel Corporation |
Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
|
|
US6868476B2
(en)
|
2001-08-27 |
2005-03-15 |
Intel Corporation |
Software controlled content addressable memory in a general purpose execution datapath
|
|
US7487505B2
(en)
*
|
2001-08-27 |
2009-02-03 |
Intel Corporation |
Multithreaded microprocessor with register allocation based on number of active threads
|
|
US7610451B2
(en)
*
|
2002-01-25 |
2009-10-27 |
Intel Corporation |
Data transfer mechanism using unidirectional pull bus and push bus
|
|
US7437724B2
(en)
|
2002-04-03 |
2008-10-14 |
Intel Corporation |
Registers for data transfers
|
|
US7337275B2
(en)
*
|
2002-08-13 |
2008-02-26 |
Intel Corporation |
Free list and ring data structure management
|
|
US6941438B2
(en)
|
2003-01-10 |
2005-09-06 |
Intel Corporation |
Memory interleaving
|