JPS55178894U - - Google Patents

Info

Publication number
JPS55178894U
JPS55178894U JP7650779U JP7650779U JPS55178894U JP S55178894 U JPS55178894 U JP S55178894U JP 7650779 U JP7650779 U JP 7650779U JP 7650779 U JP7650779 U JP 7650779U JP S55178894 U JPS55178894 U JP S55178894U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7650779U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7650779U priority Critical patent/JPS55178894U/ja
Publication of JPS55178894U publication Critical patent/JPS55178894U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
JP7650779U 1979-06-07 1979-06-07 Pending JPS55178894U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7650779U JPS55178894U (zh) 1979-06-07 1979-06-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7650779U JPS55178894U (zh) 1979-06-07 1979-06-07

Publications (1)

Publication Number Publication Date
JPS55178894U true JPS55178894U (zh) 1980-12-22

Family

ID=29310006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7650779U Pending JPS55178894U (zh) 1979-06-07 1979-06-07

Country Status (1)

Country Link
JP (1) JPS55178894U (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08288475A (ja) * 1996-05-20 1996-11-01 Hitachi Ltd 半導体記憶装置の製造方法
JPH09107085A (ja) * 1996-09-17 1997-04-22 Hitachi Ltd 半導体記憶装置
US7196368B2 (en) 1995-11-20 2007-03-27 Renesas Technology Corp. Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196368B2 (en) 1995-11-20 2007-03-27 Renesas Technology Corp. Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film
JPH08288475A (ja) * 1996-05-20 1996-11-01 Hitachi Ltd 半導体記憶装置の製造方法
JPH09107085A (ja) * 1996-09-17 1997-04-22 Hitachi Ltd 半導体記憶装置

Similar Documents

Publication Publication Date Title
BR8006808A (zh)
FR2446433B1 (zh)
DE2952414C2 (zh)
FR2446068B1 (zh)
JPS55178894U (zh)
FR2448942B2 (zh)
FR2449105B1 (zh)
AT364253B (zh)
FR2449032B1 (zh)
AU79557S (zh)
AU79558S (zh)
AU78270S (zh)
AU80228S (zh)
AU79200S (zh)
AU78386S (zh)
AU78389S (zh)
AU77763S (zh)
AU79826S (zh)
AU79559S (zh)
AU78385S (zh)
AU78271S (zh)
AU77669S (zh)
AU79918S (zh)
AU79950S (zh)
BG44802A1 (zh)