JPS55163456A - F-dc circuit for speed meter - Google Patents

F-dc circuit for speed meter

Info

Publication number
JPS55163456A
JPS55163456A JP7162579A JP7162579A JPS55163456A JP S55163456 A JPS55163456 A JP S55163456A JP 7162579 A JP7162579 A JP 7162579A JP 7162579 A JP7162579 A JP 7162579A JP S55163456 A JPS55163456 A JP S55163456A
Authority
JP
Japan
Prior art keywords
speed
pulse
atc
wheel
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7162579A
Other languages
Japanese (ja)
Other versions
JPS6059544B2 (en
Inventor
Hiroichi Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7162579A priority Critical patent/JPS6059544B2/en
Publication of JPS55163456A publication Critical patent/JPS55163456A/en
Publication of JPS6059544B2 publication Critical patent/JPS6059544B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Electric Propulsion And Braking For Vehicles (AREA)

Abstract

PURPOSE: To reduce the number of parts by a method wherein a circuit is commonly used for an ATC control device and the correction of a wheel of a driving circuit in a speed meter.
CONSTITUTION: A standard pulse 1 is distributed to standard speed pulses 20, 21,...2nkm/H corrected by the diameter of a wheel by means of a pulse distributor 2 and a wheel diameter switch 3. Furthermore, an ATC pattern gate 4 synthsizes the standard speed pulse corresponding to the speed control signal from an ATC receiver 7, and compares 5 it with the speed pulse from a speed generator 8 making an ATC pattern pulse. If the car speed exceeds the ATC control speed, an output relay FBR falls and produces a brake instruction. The output of the aforementioned speed pulse and an up-down counter 14 is compared 13 with that of the speed generator 8, so that a speed meter 16 is driven in such a way that the condition of the up-down counter 14 corresponds to the speed.
COPYRIGHT: (C)1980,JPO&Japio
JP7162579A 1979-06-06 1979-06-06 F-DC circuit for speedometer Expired JPS6059544B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7162579A JPS6059544B2 (en) 1979-06-06 1979-06-06 F-DC circuit for speedometer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7162579A JPS6059544B2 (en) 1979-06-06 1979-06-06 F-DC circuit for speedometer

Publications (2)

Publication Number Publication Date
JPS55163456A true JPS55163456A (en) 1980-12-19
JPS6059544B2 JPS6059544B2 (en) 1985-12-25

Family

ID=13466015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7162579A Expired JPS6059544B2 (en) 1979-06-06 1979-06-06 F-DC circuit for speedometer

Country Status (1)

Country Link
JP (1) JPS6059544B2 (en)

Also Published As

Publication number Publication date
JPS6059544B2 (en) 1985-12-25

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