JPS55160884A - Global watch - Google Patents

Global watch

Info

Publication number
JPS55160884A
JPS55160884A JP2624180A JP2624180A JPS55160884A JP S55160884 A JPS55160884 A JP S55160884A JP 2624180 A JP2624180 A JP 2624180A JP 2624180 A JP2624180 A JP 2624180A JP S55160884 A JPS55160884 A JP S55160884A
Authority
JP
Japan
Prior art keywords
circuit
time lag
fed
gate
correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2624180A
Other languages
Japanese (ja)
Other versions
JPS5757671B2 (en
Inventor
Shingo Ichikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP2624180A priority Critical patent/JPS55160884A/en
Publication of JPS55160884A publication Critical patent/JPS55160884A/en
Publication of JPS5757671B2 publication Critical patent/JPS5757671B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electromechanical Clocks (AREA)
  • Electric Clocks (AREA)

Abstract

PURPOSE: To obtain a global watch with hand indication by correcting the time range preset by a single switch operation.
CONSTITUTION: The time lag correcting switch 9 sets the flipflop circuit 11 as the corrective memory circuit by the output of the logic differentiation circuit when it is closed. This opens the AND gate 12 to allow the time lag correcting signal (for instance 32Hz) of the divider circuit 2 to be fed to the drive circuit 4 passing through the OR gate 3. The output of the AND gate is fed to the counter 13 as the time lag counter. When the number of counting reaches the preset value according to the unit of the time lag, the FF circuit 11 is reset. Thus, only pulses of the number preset is fed to the drive circuit 4 to perform time lag correction.
COPYRIGHT: (C)1980,JPO&Japio
JP2624180A 1980-03-03 1980-03-03 Global watch Granted JPS55160884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2624180A JPS55160884A (en) 1980-03-03 1980-03-03 Global watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2624180A JPS55160884A (en) 1980-03-03 1980-03-03 Global watch

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP5185874A Division JPS57946B2 (en) 1974-05-10 1974-05-10

Publications (2)

Publication Number Publication Date
JPS55160884A true JPS55160884A (en) 1980-12-15
JPS5757671B2 JPS5757671B2 (en) 1982-12-06

Family

ID=12187799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2624180A Granted JPS55160884A (en) 1980-03-03 1980-03-03 Global watch

Country Status (1)

Country Link
JP (1) JPS55160884A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4841913A (en) * 1971-10-04 1973-06-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4841913A (en) * 1971-10-04 1973-06-19

Also Published As

Publication number Publication date
JPS5757671B2 (en) 1982-12-06

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