JPS55158651A - Molding method for package of semiconductor - Google Patents
Molding method for package of semiconductorInfo
- Publication number
- JPS55158651A JPS55158651A JP6640979A JP6640979A JPS55158651A JP S55158651 A JPS55158651 A JP S55158651A JP 6640979 A JP6640979 A JP 6640979A JP 6640979 A JP6640979 A JP 6640979A JP S55158651 A JPS55158651 A JP S55158651A
- Authority
- JP
- Japan
- Prior art keywords
- package
- horns
- vibration
- laminar
- thermoplastic resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000000465 moulding Methods 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 229920005992 thermoplastic resin Polymers 0.000 abstract 2
- 101150114468 TUB1 gene Proteins 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 238000007373 indentation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lining Or Joining Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6640979A JPS55158651A (en) | 1979-05-28 | 1979-05-28 | Molding method for package of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6640979A JPS55158651A (en) | 1979-05-28 | 1979-05-28 | Molding method for package of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55158651A true JPS55158651A (en) | 1980-12-10 |
| JPS6142862B2 JPS6142862B2 (enrdf_load_stackoverflow) | 1986-09-24 |
Family
ID=13314961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6640979A Granted JPS55158651A (en) | 1979-05-28 | 1979-05-28 | Molding method for package of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55158651A (enrdf_load_stackoverflow) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263449A (ja) * | 1986-08-01 | 1987-03-20 | Hitachi Ltd | 半導体装置の製造法 |
-
1979
- 1979-05-28 JP JP6640979A patent/JPS55158651A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6263449A (ja) * | 1986-08-01 | 1987-03-20 | Hitachi Ltd | 半導体装置の製造法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6142862B2 (enrdf_load_stackoverflow) | 1986-09-24 |
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