JPS55147859A - Communication controlling system - Google Patents

Communication controlling system

Info

Publication number
JPS55147859A
JPS55147859A JP5554279A JP5554279A JPS55147859A JP S55147859 A JPS55147859 A JP S55147859A JP 5554279 A JP5554279 A JP 5554279A JP 5554279 A JP5554279 A JP 5554279A JP S55147859 A JPS55147859 A JP S55147859A
Authority
JP
Japan
Prior art keywords
physical addresses
lines
addresses
scanning unit
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5554279A
Other languages
Japanese (ja)
Inventor
Motojiro Nishio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5554279A priority Critical patent/JPS55147859A/en
Publication of JPS55147859A publication Critical patent/JPS55147859A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To process a large number of lines with a small hardware, by providing a line scanning unit where double definition without fixing physical addresses on logical addresses and time division operations are possible. CONSTITUTION:Before transmission and receiving operatins, the CPU initializes physical addresses of the group of line adapters LA205. Physical addresses from the CPU which are set onto logical addresses of memories corresponding to lines in the line control part are led out by line scanning unit 204. Scanning unit 204 reads out logical addresses of memories corresponding to lines while selecting them successively even if many multiplex communication control units are connected, and unit 204 transfers physical addresses led out from them to LA205 in time division.
JP5554279A 1979-05-07 1979-05-07 Communication controlling system Pending JPS55147859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5554279A JPS55147859A (en) 1979-05-07 1979-05-07 Communication controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5554279A JPS55147859A (en) 1979-05-07 1979-05-07 Communication controlling system

Publications (1)

Publication Number Publication Date
JPS55147859A true JPS55147859A (en) 1980-11-18

Family

ID=13001595

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5554279A Pending JPS55147859A (en) 1979-05-07 1979-05-07 Communication controlling system

Country Status (1)

Country Link
JP (1) JPS55147859A (en)

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