JPS55138153A - Computer supervisory unit - Google Patents

Computer supervisory unit

Info

Publication number
JPS55138153A
JPS55138153A JP4537279A JP4537279A JPS55138153A JP S55138153 A JPS55138153 A JP S55138153A JP 4537279 A JP4537279 A JP 4537279A JP 4537279 A JP4537279 A JP 4537279A JP S55138153 A JPS55138153 A JP S55138153A
Authority
JP
Japan
Prior art keywords
information
main memory
display unit
access mechanism
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4537279A
Other languages
Japanese (ja)
Inventor
Minoru Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4537279A priority Critical patent/JPS55138153A/en
Publication of JPS55138153A publication Critical patent/JPS55138153A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to grasp the operation state of a system all the time via a display unit by reading and analyzing information in the main memory unit of a computer at a constant period asynchronously with computing processing by a direct access memory system and then by displaying the result on the display unit.
CONSTITUTION: To the main memory unit, direct memory access mechanism 4 is connected and to this access mechanism 4, memory 3 is connected which has collected-information storage table 32 and information collecting table 31 stored with read addresses, a conversion processing method, a display method, etc. Then, an interruption is supplied from periodic timer 2 to microprocessor 1 and logic 1 is set in a processing counter; and information corresponding to the value set in the counter is read out from table 31 via access mechanism 4 and on the basis of a main memory address, information in the main memory unit is read out. According to the contents of table 31, processing comes into effect to set information in table 32 and the contents set to this table 32 are displayed on display unit 5, thereby grasping all the time the operation state of this system.
COPYRIGHT: (C)1980,JPO&Japio
JP4537279A 1979-04-16 1979-04-16 Computer supervisory unit Pending JPS55138153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4537279A JPS55138153A (en) 1979-04-16 1979-04-16 Computer supervisory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4537279A JPS55138153A (en) 1979-04-16 1979-04-16 Computer supervisory unit

Publications (1)

Publication Number Publication Date
JPS55138153A true JPS55138153A (en) 1980-10-28

Family

ID=12717432

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4537279A Pending JPS55138153A (en) 1979-04-16 1979-04-16 Computer supervisory unit

Country Status (1)

Country Link
JP (1) JPS55138153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132261A (en) * 1983-12-21 1985-07-15 Hitachi Ltd Displaying system of business program symbol name in terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60132261A (en) * 1983-12-21 1985-07-15 Hitachi Ltd Displaying system of business program symbol name in terminal

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