JPS55138139A - Signal collecting circuit system - Google Patents

Signal collecting circuit system

Info

Publication number
JPS55138139A
JPS55138139A JP4431379A JP4431379A JPS55138139A JP S55138139 A JPS55138139 A JP S55138139A JP 4431379 A JP4431379 A JP 4431379A JP 4431379 A JP4431379 A JP 4431379A JP S55138139 A JPS55138139 A JP S55138139A
Authority
JP
Japan
Prior art keywords
signal
converter
processor
gain
magnitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4431379A
Other languages
Japanese (ja)
Inventor
Tadao Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4431379A priority Critical patent/JPS55138139A/en
Publication of JPS55138139A publication Critical patent/JPS55138139A/en
Pending legal-status Critical Current

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  • Other Investigation Or Analysis Of Materials By Electrical Means (AREA)

Abstract

PURPOSE: To reduce quantization errors by processing a digital signal obtained by A/D converting after making nealry constant the magnitude of the signal by a variable gain amplifier.
CONSTITUTION: To process by processor 4 input signal 1 varying magnitude, control command 8 needed to collect signal 1 is supplied from processor 4 to timing controller 7. Controller 7 supplies timing signal 10 to gain control signal generating circuit 6 which generates control signal 11 controlling the gain of variable gain amplifier 5 and also synchronizes with signal 10 to supply timing pulse 9 operating converter 3 to A/D converter 3. Then, the gain of amplifier 5 is controlled by control signal 11 generated by generating circuit 6 to make nearly constant the magnitude of a signal applied to converter 3, which converts it into a digital signal, and converter 3 is put into operation of effectiveness and high precision to reduce errors of the quantization of processor 4.
COPYRIGHT: (C)1980,JPO&Japio
JP4431379A 1979-04-13 1979-04-13 Signal collecting circuit system Pending JPS55138139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4431379A JPS55138139A (en) 1979-04-13 1979-04-13 Signal collecting circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4431379A JPS55138139A (en) 1979-04-13 1979-04-13 Signal collecting circuit system

Publications (1)

Publication Number Publication Date
JPS55138139A true JPS55138139A (en) 1980-10-28

Family

ID=12687988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4431379A Pending JPS55138139A (en) 1979-04-13 1979-04-13 Signal collecting circuit system

Country Status (1)

Country Link
JP (1) JPS55138139A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193939A (en) * 1984-10-13 1986-05-12 Jeol Ltd Nuclear magnetic resonator
US6091301A (en) * 1996-06-03 2000-07-18 Scientific-Atlanta, Inc. Flatness compensation of diplex filter roll-off using active amplifier peaking circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6193939A (en) * 1984-10-13 1986-05-12 Jeol Ltd Nuclear magnetic resonator
US6091301A (en) * 1996-06-03 2000-07-18 Scientific-Atlanta, Inc. Flatness compensation of diplex filter roll-off using active amplifier peaking circuit

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