JPS55132156A - Clock reproducer - Google Patents
Clock reproducerInfo
- Publication number
- JPS55132156A JPS55132156A JP3965979A JP3965979A JPS55132156A JP S55132156 A JPS55132156 A JP S55132156A JP 3965979 A JP3965979 A JP 3965979A JP 3965979 A JP3965979 A JP 3965979A JP S55132156 A JPS55132156 A JP S55132156A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- signal processing
- component
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To obtain a clock reproducer which makes no error in signal processing by sending a regenerated clock signal with a few phase errors to a discriminating circuit and that, low in occurrence frequencies of cycle skips and false zero crossings, to a signal processing circuit. CONSTITUTION:Clock signal frequency component b extracted from received signal a by clock extractor 8 is branched by branching circuit 9. Signal component b1, on the other hand, has its unneeded component removed by the 1st tank circuit 10 and limiter circuit 11 band-limits it to obtain the 1st regenerated clock signal d1, which is sent to discriminating circuit 12. Selectivity Q of tank circuit 10 is so set that a phase error will be minimized, and the discriminating process of circuit 12 is performed excellently. Signal component b2 is passed through tank circuit 13 and limiter circuit 14 to extract regenerated clock signal d2, which is sent to signal processing circuit 15. Selectivity Q of circuit 13 is so set that the occurence frequencies of cycle skips and false zero-corrosings will be minimized. The signal processing of circuit 15, therefore, causes no error.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54039659A JPS6019860B2 (en) | 1979-04-02 | 1979-04-02 | clock regenerator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54039659A JPS6019860B2 (en) | 1979-04-02 | 1979-04-02 | clock regenerator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55132156A true JPS55132156A (en) | 1980-10-14 |
JPS6019860B2 JPS6019860B2 (en) | 1985-05-18 |
Family
ID=12559204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54039659A Expired JPS6019860B2 (en) | 1979-04-02 | 1979-04-02 | clock regenerator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6019860B2 (en) |
-
1979
- 1979-04-02 JP JP54039659A patent/JPS6019860B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6019860B2 (en) | 1985-05-18 |
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