JPS55131849A - Microprogram controller - Google Patents

Microprogram controller

Info

Publication number
JPS55131849A
JPS55131849A JP3915679A JP3915679A JPS55131849A JP S55131849 A JPS55131849 A JP S55131849A JP 3915679 A JP3915679 A JP 3915679A JP 3915679 A JP3915679 A JP 3915679A JP S55131849 A JPS55131849 A JP S55131849A
Authority
JP
Japan
Prior art keywords
register
circuit
macroinstructions
address
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3915679A
Other languages
Japanese (ja)
Inventor
Kenichi Tsukioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3915679A priority Critical patent/JPS55131849A/en
Publication of JPS55131849A publication Critical patent/JPS55131849A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To form efficiently a program of macroinstructions of a system, by changing operations of specific macroinstructions according to the content of a comparing register.
CONSTITUTION: In comparing register 5, instruction codes of specific macroinstructions are stored by macroinstructions and when macroinstructions are executed one after another, a macroinstruction insluding the same instruction code as the content of register 5 is stored in macroinstruction register 2, and in this case, converterd by decoder circuit 15 into the intial address of control storage 1, which is sent to address selecting circuit 8. The address outputted to circuit 8 is used to read and send an execution microinstruction to microinstruction register 4 and at the same time, "+1" is added to the address by "+1" adding circuit 16, whose output is stored in control memory address register 3. When the macroinstruction is stored in register 4, the microinstruction exercising output control over comparing circuit 6 allows the output to supply a permission signal to AND circuit 9.
COPYRIGHT: (C)1980,JPO&Japio
JP3915679A 1979-03-30 1979-03-30 Microprogram controller Pending JPS55131849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3915679A JPS55131849A (en) 1979-03-30 1979-03-30 Microprogram controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3915679A JPS55131849A (en) 1979-03-30 1979-03-30 Microprogram controller

Publications (1)

Publication Number Publication Date
JPS55131849A true JPS55131849A (en) 1980-10-14

Family

ID=12545240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3915679A Pending JPS55131849A (en) 1979-03-30 1979-03-30 Microprogram controller

Country Status (1)

Country Link
JP (1) JPS55131849A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917150A (en) * 1972-05-22 1974-02-15
JPS5245232A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Micro program modification circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4917150A (en) * 1972-05-22 1974-02-15
JPS5245232A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Micro program modification circuit

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