JPS55123719A - Data input circuit - Google Patents

Data input circuit

Info

Publication number
JPS55123719A
JPS55123719A JP3089279A JP3089279A JPS55123719A JP S55123719 A JPS55123719 A JP S55123719A JP 3089279 A JP3089279 A JP 3089279A JP 3089279 A JP3089279 A JP 3089279A JP S55123719 A JPS55123719 A JP S55123719A
Authority
JP
Japan
Prior art keywords
signal
data
reset
stage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3089279A
Other languages
Japanese (ja)
Inventor
Seisaku Tate
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3089279A priority Critical patent/JPS55123719A/en
Publication of JPS55123719A publication Critical patent/JPS55123719A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To input multi-input signals effectively by holding input signals until the completion of processing operations and by resetting preceding data when a prescribed-width notification is received.
CONSTITUTION: This circuit is constituted by adding an automatic reset circuit and a data coming signal gate C to data holding circuits 21W2n. The reset circuit is equipped with FF,D and drives the T terminal of FF,D when coming signal P1 is outputted to a processing unit. At this time, data obtained by OR between the signal output of circuit 21W2n and gate E is written to the terminal of FF,D and is connected to the reset terminal of FF,D. When data comes, a pules is outputted from the preceding-stage FF of circuits 21W2n is outputted and becomes a notification signal and becomes a timing pulse simultaneously to operate OR among the OR output of the succeeding-stage FF, read processing completion signal P2, and gate F and reset the succeeding-stage FF by reset signal P3. Therefore, FF,D generates a differential pulse for data coming. Though the succeeding-stage FF is set for data signal 0→1, a new signal is held because the reset signal precedes this set.
COPYRIGHT: (C)1980,JPO&Japio
JP3089279A 1979-03-15 1979-03-15 Data input circuit Pending JPS55123719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3089279A JPS55123719A (en) 1979-03-15 1979-03-15 Data input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3089279A JPS55123719A (en) 1979-03-15 1979-03-15 Data input circuit

Publications (1)

Publication Number Publication Date
JPS55123719A true JPS55123719A (en) 1980-09-24

Family

ID=12316368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3089279A Pending JPS55123719A (en) 1979-03-15 1979-03-15 Data input circuit

Country Status (1)

Country Link
JP (1) JPS55123719A (en)

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