JPS55121781A - Video processing circuit - Google Patents

Video processing circuit

Info

Publication number
JPS55121781A
JPS55121781A JP2898379A JP2898379A JPS55121781A JP S55121781 A JPS55121781 A JP S55121781A JP 2898379 A JP2898379 A JP 2898379A JP 2898379 A JP2898379 A JP 2898379A JP S55121781 A JPS55121781 A JP S55121781A
Authority
JP
Japan
Prior art keywords
output
video
supplied
circuit
gamma correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2898379A
Other languages
Japanese (ja)
Inventor
Keiji Eda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2898379A priority Critical patent/JPS55121781A/en
Publication of JPS55121781A publication Critical patent/JPS55121781A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/57—Control of contrast or brightness

Abstract

PURPOSE:To keep the steady output of the synchronous detection circuit in the TV picture receiver even to the fluctuation of the power voltage under the correction state of the gamma correction circuit which gives the compression to the part near the white level. CONSTITUTION:The synchronous detection is carried out at video detection step 1, and the output is supplied to video amplifying circuit 3 via gamma correction circuit 2. Video detection output A receives the voltage division via resistances 11 and 12 to be supplied to circuit 2. Output A, however, maintains as it is such linearity as to damage the image at the white level side. In this connection, the power voltage is divided via resistances 17 and 18, and the bias voltage which is supplied via diode 16 is supplied. Accordingly, the gamma correction is applied from the level of nearly the center of video signal component V of the video output through the side of the white level in order to give the compression to the video signal at the white level side. At the same time, the correction start level has the change even if the power voltage may has the fluctuation, and as a result the gamma correction can always be given at the fixed position of component V.
JP2898379A 1979-03-13 1979-03-13 Video processing circuit Pending JPS55121781A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2898379A JPS55121781A (en) 1979-03-13 1979-03-13 Video processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2898379A JPS55121781A (en) 1979-03-13 1979-03-13 Video processing circuit

Publications (1)

Publication Number Publication Date
JPS55121781A true JPS55121781A (en) 1980-09-19

Family

ID=12263643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2898379A Pending JPS55121781A (en) 1979-03-13 1979-03-13 Video processing circuit

Country Status (1)

Country Link
JP (1) JPS55121781A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139614A (en) * 1974-04-24 1975-11-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139614A (en) * 1974-04-24 1975-11-08

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