JPS55118150A - Computer circuit - Google Patents

Computer circuit

Info

Publication number
JPS55118150A
JPS55118150A JP2527679A JP2527679A JPS55118150A JP S55118150 A JPS55118150 A JP S55118150A JP 2527679 A JP2527679 A JP 2527679A JP 2527679 A JP2527679 A JP 2527679A JP S55118150 A JPS55118150 A JP S55118150A
Authority
JP
Japan
Prior art keywords
rom5b
ram6
switches
alteration
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2527679A
Other languages
Japanese (ja)
Inventor
Takashi Mizuguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2527679A priority Critical patent/JPS55118150A/en
Publication of JPS55118150A publication Critical patent/JPS55118150A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To secure the simple and quick alteration of the program by installing the RAM to facilitate the alteration of the program and the address switching circuit to the computer memory circuit.
CONSTITUTION: Switches 101aW101n are provided between address decoder 4 and ROM5, and at the same time switch 102 is added between RAM6 and decoder 4 each. In the example requiring the alteration to ROM5b, first switches 101b and 102 are connected as shown by the dotted lines, and then the program contents of ROM5b are copied to RAM6 via CPU1. Then the contents of RAM6 are corrected properly with switches 101 and 102 kept in the state of the dotted line. After correction, switches 101b and 102 are switched as shown by the solid lines. As a result, no activation is given to ROM5b, and instead RAM6 is activated with the address information of ROM5b.
COPYRIGHT: (C)1980,JPO&Japio
JP2527679A 1979-03-05 1979-03-05 Computer circuit Pending JPS55118150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2527679A JPS55118150A (en) 1979-03-05 1979-03-05 Computer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2527679A JPS55118150A (en) 1979-03-05 1979-03-05 Computer circuit

Publications (1)

Publication Number Publication Date
JPS55118150A true JPS55118150A (en) 1980-09-10

Family

ID=12161491

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2527679A Pending JPS55118150A (en) 1979-03-05 1979-03-05 Computer circuit

Country Status (1)

Country Link
JP (1) JPS55118150A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794844A (en) * 1980-12-03 1982-06-12 Hitachi Ltd Data processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5794844A (en) * 1980-12-03 1982-06-12 Hitachi Ltd Data processor

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