JPS55116130A - Interception system for communication circuit - Google Patents

Interception system for communication circuit

Info

Publication number
JPS55116130A
JPS55116130A JP2361679A JP2361679A JPS55116130A JP S55116130 A JPS55116130 A JP S55116130A JP 2361679 A JP2361679 A JP 2361679A JP 2361679 A JP2361679 A JP 2361679A JP S55116130 A JPS55116130 A JP S55116130A
Authority
JP
Japan
Prior art keywords
lut
unit
mdm
inputted
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2361679A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Oba
Masakazu Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2361679A priority Critical patent/JPS55116130A/en
Publication of JPS55116130A publication Critical patent/JPS55116130A/en
Pending legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To reduce faults of frequent occurrence right after replacing a unit of an electronic computer system with a communication circuit, by verifying downward data from a replaceable unit by providing an interception verifier when replacing any other unit than a terminal.
CONSTITUTION: In a computer system with a communication circuit, two-system constitution is employed covering the units from circuit connection unit LUT higher in order than modem MDM to CPU and between LUT and MDM, interception verifier ICD is provided. Although upward data from MDM2 are inputted to LUT3 in operation by way of receiving line RD, they are intercepted halfway by receiver RCV1 of ICD and the same data are inputted to LUT4 of a replaced system via driver DRV. Although downward data from LUT3 in operation are sent to MDM2 via transmitting line SD, they are intercepted halfway by receiver RCV2 and then inputted to comparator circuit CMP. Downward data from LUT4 of the replaced system are supplied to CMP and compared there with those in operation, so that when the both disagree, a fault signal will be sent out from terminal EST. Thus, a check on the replaced unit can be made while the operation is in process.
COPYRIGHT: (C)1980,JPO&Japio
JP2361679A 1979-03-01 1979-03-01 Interception system for communication circuit Pending JPS55116130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2361679A JPS55116130A (en) 1979-03-01 1979-03-01 Interception system for communication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2361679A JPS55116130A (en) 1979-03-01 1979-03-01 Interception system for communication circuit

Publications (1)

Publication Number Publication Date
JPS55116130A true JPS55116130A (en) 1980-09-06

Family

ID=12115532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2361679A Pending JPS55116130A (en) 1979-03-01 1979-03-01 Interception system for communication circuit

Country Status (1)

Country Link
JP (1) JPS55116130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS628249A (en) * 1985-07-03 1987-01-16 Fujitsu Ltd Control system for data monitoring

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS628249A (en) * 1985-07-03 1987-01-16 Fujitsu Ltd Control system for data monitoring
JPH0375910B2 (en) * 1985-07-03 1991-12-03 Fujitsu Ltd

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