JPS55115751A - Tuning circuit for time division multiplexer - Google Patents

Tuning circuit for time division multiplexer

Info

Publication number
JPS55115751A
JPS55115751A JP1981580A JP1981580A JPS55115751A JP S55115751 A JPS55115751 A JP S55115751A JP 1981580 A JP1981580 A JP 1981580A JP 1981580 A JP1981580 A JP 1981580A JP S55115751 A JPS55115751 A JP S55115751A
Authority
JP
Japan
Prior art keywords
time division
tuning circuit
division multiplexer
multiplexer
tuning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981580A
Other languages
English (en)
Japanese (ja)
Inventor
Jiyannfuransowa Porutojiyowa
Jirubeeru Noeru
Jiyannkuroodo Birii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PORTEJOIE JEAN F
Original Assignee
PORTEJOIE JEAN F
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PORTEJOIE JEAN F filed Critical PORTEJOIE JEAN F
Publication of JPS55115751A publication Critical patent/JPS55115751A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/073—Bit stuffing, e.g. PDH

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP1981580A 1979-02-21 1980-02-21 Tuning circuit for time division multiplexer Pending JPS55115751A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7905109A FR2450008A1 (fr) 1979-02-21 1979-02-21 Circuit de synchronisation de signaux numeriques plesiochrones par justification

Publications (1)

Publication Number Publication Date
JPS55115751A true JPS55115751A (en) 1980-09-05

Family

ID=9222533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981580A Pending JPS55115751A (en) 1979-02-21 1980-02-21 Tuning circuit for time division multiplexer

Country Status (6)

Country Link
US (1) US4355387A (enExample)
JP (1) JPS55115751A (enExample)
CA (1) CA1147876A (enExample)
FR (1) FR2450008A1 (enExample)
GB (1) GB2049364B (enExample)
IT (1) IT1146930B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2500240B1 (fr) * 1981-02-19 1986-10-31 Billy Jean Claude Systeme de multiplexage et de demultiplexage avec justification
US4860285A (en) * 1987-10-21 1989-08-22 Advanced Micro Devices, Inc. Master/slave synchronizer
FR2637141A1 (fr) * 1988-09-27 1990-03-30 Alcatel Thomson Faisceaux Dispositif de traitement de signaux plesiochrones
DE3922897A1 (de) * 1989-07-12 1991-01-17 Philips Patentverwaltung Stopfentscheidungsschaltung fuer eine anordnung zur bitratenanpassung
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
IT1244350B (it) * 1990-12-21 1994-07-08 Telettra Spa Metodo per la riduzione del rumore di fase introdotto nella resincronizzazione di segnali digitali mediante giustificazione, e circuiti integrati per l'implementazione del metodo
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
EP0541288B1 (en) * 1991-11-05 1998-07-08 Fu-Chieh Hsu Circuit module redundacy architecture
DE4205959A1 (de) * 1992-02-27 1993-09-02 Philips Patentverwaltung Schaltungsanordnung zum ausgleich von frequenz- und/oder phasenschwankungen zwischen einem ankommenden und einem abgehenden signal
EP0654168B1 (en) 1992-08-10 2001-10-31 Monolithic System Technology, Inc. Fault-tolerant hierarchical bus system
US5675579A (en) * 1992-12-17 1997-10-07 Tandem Computers Incorporated Method for verifying responses to messages using a barrier message
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
DK133495A (da) * 1995-11-24 1997-05-25 Dsc Communications As Fremgangsmåde og modtagerkredsløb til desynkronisering i et digitalt transmissionssystem
FR2765427B1 (fr) * 1997-06-27 2000-09-08 Sgs Thomson Microelectronics Circuit d'emission-reception pour relier une station de base a une centrale de commande de station de base selon la norme dect
FR3094593B1 (fr) * 2019-03-29 2021-02-19 Teledyne E2V Semiconductors Sas Procédé de synchronisation de données numériques envoyées en série

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7105512A (enExample) * 1971-04-23 1972-10-25
FR2178418A5 (enExample) * 1972-03-31 1973-11-09 Peron Roger
FR2373198A1 (fr) * 1976-12-03 1978-06-30 Cit Alcatel Dispositif de multiplexage numerique de trains plesiochrones
US4095053A (en) * 1977-09-01 1978-06-13 Bell Telephone Laboratories, Incorporated Quasi-pulse stuffing synchronization
US4224473A (en) * 1978-05-31 1980-09-23 Digital Communications Corporation TDMA Multiplexer-demultiplexer with multiple ports

Also Published As

Publication number Publication date
IT8047951A0 (it) 1980-02-20
CA1147876A (en) 1983-06-07
GB2049364A (en) 1980-12-17
US4355387A (en) 1982-10-19
GB2049364B (en) 1983-02-16
IT1146930B (it) 1986-11-19
FR2450008A1 (fr) 1980-09-19
FR2450008B1 (enExample) 1983-11-18

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