JPS55112075A - Charged facsimile receiver - Google Patents
Charged facsimile receiverInfo
- Publication number
- JPS55112075A JPS55112075A JP1917379A JP1917379A JPS55112075A JP S55112075 A JPS55112075 A JP S55112075A JP 1917379 A JP1917379 A JP 1917379A JP 1917379 A JP1917379 A JP 1917379A JP S55112075 A JPS55112075 A JP S55112075A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- main body
- card
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Facsimile Transmission Control (AREA)
Abstract
PURPOSE: To eliminate the defect as well as prevent the surreptitious use for the card by securing the operation of the device with insertion of the card incorporating the same electronic circuit as the partial circuit of the main body of the facsimile receiver.
CONSTITUTION: With insertion of card 1 incorporating electronic circuit 2 into the main body, the connection is secured to the circuit within the main body via terminals 3, 4 and 8 each. Electronic circuit 6 within the main body features the same constitution as circuit 2, and generates the same output to the same input given from terminal 5. The output is compared through comparator 7 between circuits 2 and 6, and the coincidence signal is supplied to memory circuit 10 comprising set/reset FF and RSFF and others to hold the set state. Then the output of circuit 10 is supplied to counter circuit 11 which decides the working period of the device to be turned into the trigger signal for starting of the counting. Circuit 11 generates the set signal and supplies the signal to the relay from terminal 14 via amplifier 13 and in the form of the control signal, thus giving the control to the motor, the power source and the like. And when circuit 11 completes the counting along with the output inversion, the RSFF of circuit 10 is reset to stop the counting action. At the same time, the inverted signal stops the function of circuit 2 to avoid the reuse of the card.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1917379A JPS55112075A (en) | 1979-02-20 | 1979-02-20 | Charged facsimile receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1917379A JPS55112075A (en) | 1979-02-20 | 1979-02-20 | Charged facsimile receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55112075A true JPS55112075A (en) | 1980-08-29 |
JPS6222499B2 JPS6222499B2 (en) | 1987-05-18 |
Family
ID=11991953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1917379A Granted JPS55112075A (en) | 1979-02-20 | 1979-02-20 | Charged facsimile receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55112075A (en) |
-
1979
- 1979-02-20 JP JP1917379A patent/JPS55112075A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6222499B2 (en) | 1987-05-18 |
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