JPS55105752A - Information processor - Google Patents

Information processor

Info

Publication number
JPS55105752A
JPS55105752A JP1294179A JP1294179A JPS55105752A JP S55105752 A JPS55105752 A JP S55105752A JP 1294179 A JP1294179 A JP 1294179A JP 1294179 A JP1294179 A JP 1294179A JP S55105752 A JPS55105752 A JP S55105752A
Authority
JP
Japan
Prior art keywords
execution
signal
interruption
state
indicating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1294179A
Other languages
Japanese (ja)
Other versions
JPS6329293B2 (en
Inventor
Toru Yamamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1294179A priority Critical patent/JPS55105752A/en
Publication of JPS55105752A publication Critical patent/JPS55105752A/en
Publication of JPS6329293B2 publication Critical patent/JPS6329293B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To call the execution state indicating information after the end of processing and to continue the execution of the accumulated instruction, by providing the means temporarily shunting the execution state indication information indicating the execution of accumulated instruction.
CONSTITUTION: When interruption processing is taken place, the interruption control signal is at high level, and the state of the signal 25 indicating the state of execution of the present accumulated instruction is written in the shunting flip flop 56. The contents of FF54 are read out as the signal 26 from FF56 and the output is held in synchronizing with the clock pulse 500. When the interruption processing is finished, the interruption return control signal 27 is inputted to the AND gate 52 and the inputted signal 26 is again returned to FF54.
COPYRIGHT: (C)1980,JPO&Japio
JP1294179A 1979-02-07 1979-02-07 Information processor Granted JPS55105752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1294179A JPS55105752A (en) 1979-02-07 1979-02-07 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1294179A JPS55105752A (en) 1979-02-07 1979-02-07 Information processor

Publications (2)

Publication Number Publication Date
JPS55105752A true JPS55105752A (en) 1980-08-13
JPS6329293B2 JPS6329293B2 (en) 1988-06-13

Family

ID=11819301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1294179A Granted JPS55105752A (en) 1979-02-07 1979-02-07 Information processor

Country Status (1)

Country Link
JP (1) JPS55105752A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553043A (en) * 1978-06-20 1980-01-10 Matsushita Electric Ind Co Ltd Microcomputer control circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553043A (en) * 1978-06-20 1980-01-10 Matsushita Electric Ind Co Ltd Microcomputer control circuit

Also Published As

Publication number Publication date
JPS6329293B2 (en) 1988-06-13

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