JPS55104161A - Reception system of multi-frequency signal - Google Patents

Reception system of multi-frequency signal

Info

Publication number
JPS55104161A
JPS55104161A JP1039379A JP1039379A JPS55104161A JP S55104161 A JPS55104161 A JP S55104161A JP 1039379 A JP1039379 A JP 1039379A JP 1039379 A JP1039379 A JP 1039379A JP S55104161 A JPS55104161 A JP S55104161A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
signal detection
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1039379A
Other languages
Japanese (ja)
Inventor
Akira Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1039379A priority Critical patent/JPS55104161A/en
Publication of JPS55104161A publication Critical patent/JPS55104161A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To simplify the circuit constitution of rectifying circuit rectifying the reception signal and to make small the unit and economy, by providing the signal control circuit in common with the output side of each signal detection circuit and controlling the signal output of multi-signal detection circuit and controlling the signal output of multi-frequency through the output.
CONSTITUTION: FF circuit 19∼22 are provided at the output side of the signal detection circuits 7∼10, and the pulse train corresponding to the input frequency obtained with the signal detection circuits 7∼10 is read in and outputted. At the same time, the logical sum and logical product are taken with the pulse train outputted from FF circuits 19∼22 with the control signal output obtained from the signal control circuit 24 provided in common with the output side of the signal detection circuits 7∼10 and the output signal is obtained at the corresponded frequency channel through the pulse rectification to the single pulse having time length in which the input signal frequency is continued. Thus, the circuit constitution can be simplified and small size and economy can be achieved.
COPYRIGHT: (C)1980,JPO&Japio
JP1039379A 1979-02-02 1979-02-02 Reception system of multi-frequency signal Pending JPS55104161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1039379A JPS55104161A (en) 1979-02-02 1979-02-02 Reception system of multi-frequency signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1039379A JPS55104161A (en) 1979-02-02 1979-02-02 Reception system of multi-frequency signal

Publications (1)

Publication Number Publication Date
JPS55104161A true JPS55104161A (en) 1980-08-09

Family

ID=11748876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1039379A Pending JPS55104161A (en) 1979-02-02 1979-02-02 Reception system of multi-frequency signal

Country Status (1)

Country Link
JP (1) JPS55104161A (en)

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