JPS55102053A - Address comparison circuit - Google Patents

Address comparison circuit

Info

Publication number
JPS55102053A
JPS55102053A JP1008679A JP1008679A JPS55102053A JP S55102053 A JPS55102053 A JP S55102053A JP 1008679 A JP1008679 A JP 1008679A JP 1008679 A JP1008679 A JP 1008679A JP S55102053 A JPS55102053 A JP S55102053A
Authority
JP
Japan
Prior art keywords
address
comparison
circuit
logic
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1008679A
Other languages
Japanese (ja)
Inventor
Shinji Nishibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1008679A priority Critical patent/JPS55102053A/en
Publication of JPS55102053A publication Critical patent/JPS55102053A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the cost and to make high efficiency, by setting the store comparison FF circuit through the logic address and instruction pre-fetch address for comparison and setting the match FF circuit through the comparison of the logic address and the stop address.
CONSTITUTION: The scratch pad memory 17 incorporates registers including the instruction pre-fetch address 00, stop address 02, and memory error information 04, 05. At memory cycle, the stop address is read out in time sharing with the control circuit 18, it is compared with the logic address at the address comparator 14, and the match FF13 is set when the in agreement. Further, at the storage comparison, the instruction pre-fetch address 00 in the scratch pad memory 17 is read out with the control circuit 18, it is compared with the logic address at the address comparator and the storage comparison FF12 is set when in agreement, allowing the circuit to be only with one address comparator 14 and one scratch pad memory 17.
COPYRIGHT: (C)1980,JPO&Japio
JP1008679A 1979-01-31 1979-01-31 Address comparison circuit Pending JPS55102053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1008679A JPS55102053A (en) 1979-01-31 1979-01-31 Address comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1008679A JPS55102053A (en) 1979-01-31 1979-01-31 Address comparison circuit

Publications (1)

Publication Number Publication Date
JPS55102053A true JPS55102053A (en) 1980-08-04

Family

ID=11740522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1008679A Pending JPS55102053A (en) 1979-01-31 1979-01-31 Address comparison circuit

Country Status (1)

Country Link
JP (1) JPS55102053A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294553A (en) * 1985-06-24 1986-12-25 Fujitsu Ltd Instruction processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61294553A (en) * 1985-06-24 1986-12-25 Fujitsu Ltd Instruction processing system

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