JPS549454B1 - - Google Patents
Info
- Publication number
- JPS549454B1 JPS549454B1 JP5607971A JP5607971A JPS549454B1 JP S549454 B1 JPS549454 B1 JP S549454B1 JP 5607971 A JP5607971 A JP 5607971A JP 5607971 A JP5607971 A JP 5607971A JP S549454 B1 JPS549454 B1 JP S549454B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5895670A | 1970-07-28 | 1970-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS549454B1 true JPS549454B1 (ref) | 1979-04-24 |
Family
ID=22019940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5607971A Pending JPS549454B1 (ref) | 1970-07-28 | 1971-07-28 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3691359A (ref) |
| JP (1) | JPS549454B1 (ref) |
| CA (1) | CA946517A (ref) |
| GB (1) | GB1336930A (ref) |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3795880A (en) * | 1972-06-19 | 1974-03-05 | Ibm | Partial product array multiplier |
| US3814924A (en) * | 1973-03-12 | 1974-06-04 | Control Data Corp | Pipeline binary multiplier |
| US4181970A (en) * | 1973-10-08 | 1980-01-01 | Nippon Telegraph And Telephone Public Corporation | Digital attenuator for compressed PCM signals |
| US4118785A (en) * | 1973-10-08 | 1978-10-03 | Nippon Telegraph And Telephone Public Corporation | Method and apparatus for digital attenuation by pattern shifting |
| JPS5534613B2 (ref) * | 1973-10-08 | 1980-09-08 | ||
| US3887799A (en) * | 1973-12-03 | 1975-06-03 | Theodore P Lindgren | Asynchronous n bit position data shifter |
| US3950636A (en) * | 1974-01-16 | 1976-04-13 | Signetics Corporation | High speed multiplier logic circuit |
| US3919535A (en) * | 1974-08-21 | 1975-11-11 | Singer Co | Multiple addend adder and multiplier |
| FR2301870A1 (fr) | 1975-02-19 | 1976-09-17 | Majos Jacques | Circuit multiplicateur a fort debit numerique notamment pour filtre numerique |
| US4031377A (en) * | 1975-08-25 | 1977-06-21 | Nippon Gakki Seizo Kabushiki Kaisha | Fast multiplier circuit employing shift circuitry responsive to two binary numbers the sum of which approximately equals the mantissa of the multiplier |
| US4041296A (en) * | 1975-12-03 | 1977-08-09 | International Business Machines Incorp. | High-speed digital multiply-by-device |
| US4041292A (en) * | 1975-12-22 | 1977-08-09 | Honeywell Information Systems Inc. | High speed binary multiplication system employing a plurality of multiple generator circuits |
| US4034198A (en) * | 1975-12-22 | 1977-07-05 | Honeywell Information Systems, Inc. | Multiple generating register |
| US4086474A (en) * | 1976-09-30 | 1978-04-25 | Honeywell Information Systems Inc. | Multiplication technique in a data processing system |
| GB1582958A (en) * | 1977-06-09 | 1981-01-21 | Inst Maszyn Matematycznych War | Digital system for binary multiplication of a number by a sum of two numbers |
| US4168530A (en) * | 1978-02-13 | 1979-09-18 | Burroughs Corporation | Multiplication circuit using column compression |
| US4228520A (en) * | 1979-05-04 | 1980-10-14 | International Business Machines Corporation | High speed multiplier using carry-save/propagate pipeline with sparse carries |
| US4369500A (en) * | 1980-10-20 | 1983-01-18 | Motorola Inc. | High speed NXM bit digital, repeated addition type multiplying circuit |
| US4550335A (en) * | 1981-02-02 | 1985-10-29 | Rca Corporation | Compatible and hierarchical digital television system standard |
| US4455611A (en) * | 1981-05-11 | 1984-06-19 | Rca Corporation | Multiplier for multiplying n-bit number by quotient of an integer divided by an integer power of two |
| US4538239A (en) * | 1982-02-11 | 1985-08-27 | Texas Instruments Incorporated | High-speed multiplier for microcomputer used in digital signal processing system |
| US4577282A (en) * | 1982-02-22 | 1986-03-18 | Texas Instruments Incorporated | Microcomputer system for digital signal processing |
| FR2536879A1 (fr) * | 1982-11-26 | 1984-06-01 | Efcis | Multiplieur binaire rapide |
| US4748583A (en) * | 1984-09-17 | 1988-05-31 | Siemens Aktiengesellschaft | Cell-structured digital multiplier of semi-systolic construction |
| WO1988008567A1 (en) * | 1987-05-01 | 1988-11-03 | General Electric Company | Truncated product partial canonical signed digit multiplier |
| US4967388A (en) * | 1988-04-21 | 1990-10-30 | Harris Semiconductor Patents Inc. | Truncated product partial canonical signed digit multiplier |
| US5159568A (en) * | 1987-11-24 | 1992-10-27 | Digital Equipment Corporation | High speed parallel multiplier circuit |
| US5032865A (en) * | 1987-12-14 | 1991-07-16 | General Dynamics Corporation Air Defense Systems Div. | Calculating the dot product of large dimensional vectors in two's complement representation |
| US4884232A (en) * | 1987-12-14 | 1989-11-28 | General Dynamics Corp., Pomona Div. | Parallel processing circuits for high speed calculation of the dot product of large dimensional vectors |
| KR0152911B1 (ko) * | 1994-09-10 | 1998-10-15 | 문정환 | 병렬승산기 |
| US6085214A (en) * | 1997-09-04 | 2000-07-04 | Cirrus Logic, Inc. | Digital multiplier with multiplier encoding involving 3X term |
| US6183122B1 (en) * | 1997-09-04 | 2001-02-06 | Cirrus Logic, Inc. | Multiplier sign extension |
| US6959315B2 (en) * | 2001-12-27 | 2005-10-25 | Stmicroelectronics, Inc. | Self-timed digital processing circuits |
| US20090077145A1 (en) * | 2007-09-14 | 2009-03-19 | Cswitch Corporation | Reconfigurable arithmetic unit |
| RU2760628C1 (ru) * | 2021-02-25 | 2021-11-29 | Федеральное государственное бюджетное образовательное учреждение высшего образования «Юго-Западный государственный университет» (ЮЗГУ) (RU) | Способ и ассоциативное матричное устройство параллельного поиска образца по его префиксам |
-
1970
- 1970-07-28 US US58956A patent/US3691359A/en not_active Expired - Lifetime
-
1971
- 1971-06-04 CA CA114,834A patent/CA946517A/en not_active Expired
- 1971-07-21 GB GB3412071A patent/GB1336930A/en not_active Expired
- 1971-07-28 JP JP5607971A patent/JPS549454B1/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CA946517A (en) | 1974-04-30 |
| US3691359A (en) | 1972-09-12 |
| GB1336930A (en) | 1973-11-14 |