JPS5494248A - Input control system - Google Patents

Input control system

Info

Publication number
JPS5494248A
JPS5494248A JP176478A JP176478A JPS5494248A JP S5494248 A JPS5494248 A JP S5494248A JP 176478 A JP176478 A JP 176478A JP 176478 A JP176478 A JP 176478A JP S5494248 A JPS5494248 A JP S5494248A
Authority
JP
Japan
Prior art keywords
signal
unit
cpu
input mode
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP176478A
Other languages
Japanese (ja)
Other versions
JPS6041778B2 (en
Inventor
Shichiro Tsuruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP176478A priority Critical patent/JPS6041778B2/en
Publication of JPS5494248A publication Critical patent/JPS5494248A/en
Publication of JPS6041778B2 publication Critical patent/JPS6041778B2/en
Expired legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To perform sure signal transfer, by suitably setting the count depending on the signal delivery time by the signal line length tying between CPU and external unit, outputting the N times input mode signal to the external unit from CPU, and inputting the signal from external unit to CPU.
CONSTITUTION: The input control unit 1 fetches the signal transferred from the external unit 2 to internal while the input mode signal is outputted. The arrival of the first input mode signal having the N notation count circuit 3 and outputted from the input controller, outputs the transferred signal to the unit 1, and the unit 2 is given, which is constituted so that the transfer signal continues to be outputted until the N times input mode signal is finished to reach. Further, depending on the signal delivery time due to the signal line length tying two units, the count N is suitably set and the N times input mode signal is outputted from the unit 1 to the unit 2, allowing to input the signal transferred from the unit 2 to the unit 1. Thus, if the distance between CPU and the unit 2 is longer, the signal can surely be transferred from the unit 2 to CPU.
COPYRIGHT: (C)1979,JPO&Japio
JP176478A 1978-01-10 1978-01-10 Input control method Expired JPS6041778B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP176478A JPS6041778B2 (en) 1978-01-10 1978-01-10 Input control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP176478A JPS6041778B2 (en) 1978-01-10 1978-01-10 Input control method

Publications (2)

Publication Number Publication Date
JPS5494248A true JPS5494248A (en) 1979-07-25
JPS6041778B2 JPS6041778B2 (en) 1985-09-18

Family

ID=11510641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP176478A Expired JPS6041778B2 (en) 1978-01-10 1978-01-10 Input control method

Country Status (1)

Country Link
JP (1) JPS6041778B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55119889U (en) * 1979-02-19 1980-08-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55119889U (en) * 1979-02-19 1980-08-25

Also Published As

Publication number Publication date
JPS6041778B2 (en) 1985-09-18

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