JPS5488107A - Bit string forming and processing method - Google Patents

Bit string forming and processing method

Info

Publication number
JPS5488107A
JPS5488107A JP15685177A JP15685177A JPS5488107A JP S5488107 A JPS5488107 A JP S5488107A JP 15685177 A JP15685177 A JP 15685177A JP 15685177 A JP15685177 A JP 15685177A JP S5488107 A JPS5488107 A JP S5488107A
Authority
JP
Japan
Prior art keywords
pattern
content
becomes
inputted
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15685177A
Other languages
Japanese (ja)
Other versions
JPS5946049B2 (en
Inventor
Osamu Kanzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15685177A priority Critical patent/JPS5946049B2/en
Publication of JPS5488107A publication Critical patent/JPS5488107A/en
Publication of JPS5946049B2 publication Critical patent/JPS5946049B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)

Abstract

PURPOSE: To save bit pattern string generating circuits corresponding to the kinds of address marks by preparing a spare bit string in data signal strings.
CONSTITUTION: In the period when pattern D7 is inputted to an arithmetic circuit part 14, a gate 22 is held turned ON. Hence, the content of a register 15 becomes 0 and the content of a timing matching circut 16 becomes D7. Next, when pattern FC is inputted, the content of the register 15 becomes FC and the content of the circuit 16 is held at D7. Next, when pattern 00 is inputted, the content of the register 15 becomes 00 and the pattern FC is outputted. In synchronization to this period, the pattern D7 is outputted from the circuit 16.
COPYRIGHT: (C)1979,JPO&Japio
JP15685177A 1977-12-26 1977-12-26 Bit string generation processing method Expired JPS5946049B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15685177A JPS5946049B2 (en) 1977-12-26 1977-12-26 Bit string generation processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15685177A JPS5946049B2 (en) 1977-12-26 1977-12-26 Bit string generation processing method

Publications (2)

Publication Number Publication Date
JPS5488107A true JPS5488107A (en) 1979-07-13
JPS5946049B2 JPS5946049B2 (en) 1984-11-10

Family

ID=15636756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15685177A Expired JPS5946049B2 (en) 1977-12-26 1977-12-26 Bit string generation processing method

Country Status (1)

Country Link
JP (1) JPS5946049B2 (en)

Also Published As

Publication number Publication date
JPS5946049B2 (en) 1984-11-10

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