JPS548266B1 - - Google Patents
Info
- Publication number
- JPS548266B1 JPS548266B1 JP4984071A JP4984071A JPS548266B1 JP S548266 B1 JPS548266 B1 JP S548266B1 JP 4984071 A JP4984071 A JP 4984071A JP 4984071 A JP4984071 A JP 4984071A JP S548266 B1 JPS548266 B1 JP S548266B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
- Information Transfer Systems (AREA)
- Computer And Data Communications (AREA)
- Image Input (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5251470A | 1970-07-06 | 1970-07-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS548266B1 true JPS548266B1 (enExample) | 1979-04-13 |
Family
ID=21978107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4984071A Pending JPS548266B1 (enExample) | 1970-07-06 | 1971-07-05 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3680055A (enExample) |
| JP (1) | JPS548266B1 (enExample) |
| BE (1) | BE769573A (enExample) |
| CA (1) | CA946981A (enExample) |
| DE (1) | DE2133661C2 (enExample) |
| FR (1) | FR2100309A5 (enExample) |
| GB (1) | GB1356287A (enExample) |
| NL (1) | NL175470C (enExample) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3909526A (en) * | 1972-04-20 | 1975-09-30 | Mi 2 74245 76919720420013 781 | Square wave oscillator for a data terminal |
| US3781817A (en) * | 1972-04-20 | 1973-12-25 | Design Elements Inc | Restraint signal generator and oscillator |
| FR2216884A5 (enExample) * | 1973-02-01 | 1974-08-30 | Etudes Realis Electronique | |
| GB1499184A (en) * | 1974-04-13 | 1978-01-25 | Mathematik & Datenverarbeitung | Circuit arrangement for monitoring the state of memory segments |
| US4130868A (en) * | 1977-04-12 | 1978-12-19 | International Business Machines Corporation | Independently controllable multiple address registers for a data processor |
| US4298954A (en) * | 1979-04-30 | 1981-11-03 | International Business Machines Corporation | Alternating data buffers when one buffer is empty and another buffer is variably full of data |
| HU180133B (en) * | 1980-05-07 | 1983-02-28 | Szamitastech Koord | Equipment for displaying and storing tv picture information by means of useiof a computer access memory |
| US4644463A (en) * | 1982-12-07 | 1987-02-17 | Burroughs Corporation | System for regulating data transfer operations |
| JPS6093513A (ja) * | 1983-10-27 | 1985-05-25 | Fanuc Ltd | 数値制御装置におけるアプリケ−シヨンシステムのデ−タ入出力器 |
| US4956808A (en) * | 1985-01-07 | 1990-09-11 | International Business Machines Corporation | Real time data transformation and transmission overlapping device |
| US4881163A (en) * | 1986-09-19 | 1989-11-14 | Amdahl Corporation | Computer system architecture employing cache data line move-out queue buffer |
| GB2200483B (en) * | 1987-01-22 | 1991-10-16 | Nat Semiconductor Corp | Memory referencing in a high performance microprocessor |
| FR2642214B1 (fr) * | 1988-12-30 | 1992-11-20 | Cit Alcatel | Systeme de detection d'ecrasement de donnees dans une memoire tampon, notamment pour un commutateur de donnees |
| GB2231981A (en) * | 1989-04-27 | 1990-11-28 | Stc Plc | Memory read/write arrangement |
| KR0176537B1 (ko) * | 1995-10-14 | 1999-05-01 | 김광호 | 가변길이복호화기의 메모리 인터페이스방법 및 회로 |
| TW463481B (en) * | 1999-04-28 | 2001-11-11 | Fujitsu Ltd | Cell search method, communication synchronization apparatus, portable terminal apparatus, and recording medium |
| US6408348B1 (en) | 1999-08-20 | 2002-06-18 | International Business Machines Corporation | System, method, and program for managing I/O requests to a storage device |
| US20060004904A1 (en) * | 2004-06-30 | 2006-01-05 | Intel Corporation | Method, system, and program for managing transmit throughput for a network controller |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2817072A (en) * | 1954-08-02 | 1957-12-17 | Rca Corp | Serial memory system |
| US2907004A (en) * | 1954-10-29 | 1959-09-29 | Rca Corp | Serial memory |
| US3059221A (en) * | 1956-12-03 | 1962-10-16 | Rca Corp | Information storage and transfer system |
| US3012230A (en) * | 1957-09-30 | 1961-12-05 | Electronic Eng Co | Computer format control buffer |
| US3302185A (en) * | 1964-01-20 | 1967-01-31 | Jr Andrew P Cox | Flexible logic circuits for buffer memory |
| DE1247050B (de) * | 1964-11-25 | 1967-08-10 | Telefunken Patent | Einrichtung mit einem Pufferspeicher zur Weitergabe unregelmaessig anfallender Digitaldaten in gleichmaessigen Zeitabstaenden |
| US3421147A (en) * | 1965-05-07 | 1969-01-07 | Bell Telephone Labor Inc | Buffer arrangement |
| US3541531A (en) * | 1967-02-07 | 1970-11-17 | Bell Telephone Labor Inc | Semiconductive memory array wherein operating power is supplied via information paths |
| US3540010A (en) * | 1968-08-27 | 1970-11-10 | Bell Telephone Labor Inc | Diode-coupled semiconductive memory |
-
1970
- 1970-07-06 US US52514A patent/US3680055A/en not_active Expired - Lifetime
-
1971
- 1971-07-05 JP JP4984071A patent/JPS548266B1/ja active Pending
- 1971-07-05 CA CA117,343A patent/CA946981A/en not_active Expired
- 1971-07-06 FR FR7124675A patent/FR2100309A5/fr not_active Expired
- 1971-07-06 DE DE2133661A patent/DE2133661C2/de not_active Expired
- 1971-07-06 BE BE769573A patent/BE769573A/xx not_active IP Right Cessation
- 1971-07-06 GB GB3175771A patent/GB1356287A/en not_active Expired
- 1971-07-06 NL NLAANVRAGE7109296,A patent/NL175470C/xx not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| BE769573A (fr) | 1971-11-16 |
| DE2133661A1 (de) | 1972-01-20 |
| GB1356287A (en) | 1974-06-12 |
| US3680055A (en) | 1972-07-25 |
| FR2100309A5 (enExample) | 1972-03-17 |
| CA946981A (en) | 1974-05-07 |
| NL175470C (nl) | 1984-11-01 |
| NL7109296A (enExample) | 1972-01-10 |
| DE2133661C2 (de) | 1983-09-08 |