JPS5476117A - Diagnosis system of error correction circuit - Google Patents

Diagnosis system of error correction circuit

Info

Publication number
JPS5476117A
JPS5476117A JP14258777A JP14258777A JPS5476117A JP S5476117 A JPS5476117 A JP S5476117A JP 14258777 A JP14258777 A JP 14258777A JP 14258777 A JP14258777 A JP 14258777A JP S5476117 A JPS5476117 A JP S5476117A
Authority
JP
Japan
Prior art keywords
signal
error correction
error
track
pointer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14258777A
Other languages
Japanese (ja)
Inventor
Hisashi Kimura
Akihiro Hayakawa
Hiroshi Ichii
Kiyoo Moroto
Hirotoshi Koketsu
Hidehiko Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14258777A priority Critical patent/JPS5476117A/en
Publication of JPS5476117A publication Critical patent/JPS5476117A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To facilitate diagnosis of an error track pointer by setting all the error correction track signals formed from syndromes at a constant value and forcefully applying the correction instruction signal of an error over two tracks.
CONSTITUTION: When a pointer diagnosis signal I is applied, the outputs of a syndrome comparator 3, i.e., error correction track signals B, all become the signal of a preset value, e.g., all "1". At the same time, an inversion signal is applied to AND 4 via NOT 16 and therefore the AND 4 is held de-energized during this time. Further the signal I is applied to AND 5 via OR 14 and two track errors occur and it becomes as if the error correction signal H has been applied to the AND 5. Hence, in this case, all the error correction track signals B become a specified value, all "1" signal, etc. and therefore, the error correction signal D' becomes based only on the output signal F of an error track pointer 11 and if the data E having been error- corrected by the signal D' is examined, the diagnosis of the pointer 11 may be performed.
COPYRIGHT: (C)1979,JPO&Japio
JP14258777A 1977-11-30 1977-11-30 Diagnosis system of error correction circuit Pending JPS5476117A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14258777A JPS5476117A (en) 1977-11-30 1977-11-30 Diagnosis system of error correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14258777A JPS5476117A (en) 1977-11-30 1977-11-30 Diagnosis system of error correction circuit

Publications (1)

Publication Number Publication Date
JPS5476117A true JPS5476117A (en) 1979-06-18

Family

ID=15318768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14258777A Pending JPS5476117A (en) 1977-11-30 1977-11-30 Diagnosis system of error correction circuit

Country Status (1)

Country Link
JP (1) JPS5476117A (en)

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