JPS5475941A - Control system for memory unit - Google Patents

Control system for memory unit

Info

Publication number
JPS5475941A
JPS5475941A JP14340177A JP14340177A JPS5475941A JP S5475941 A JPS5475941 A JP S5475941A JP 14340177 A JP14340177 A JP 14340177A JP 14340177 A JP14340177 A JP 14340177A JP S5475941 A JPS5475941 A JP S5475941A
Authority
JP
Japan
Prior art keywords
memory
unit
signal
circuit
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14340177A
Other languages
Japanese (ja)
Inventor
Saburo Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14340177A priority Critical patent/JPS5475941A/en
Publication of JPS5475941A publication Critical patent/JPS5475941A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To increase the information transfer speed between the memory unit and the requested unit, by splitting the memory unit of random access into a plurality of memory modules, and by providing the circuit group corresponding to each module and common sharing circuit group. CONSTITUTION:The request unit 1 continuously delivers two memory access requests and the simultaneous operation disignation signal on the signal line 53. Two memory access request signals, address information and memory information are delivered to the signal lines 30 to 32 in time-sharing manner, and are distributed to the circuit groups 12 to 17 corresponding to the memory element groups 2 and 4 via the distribution circuits 8 to 9. When the operation designation circuit 11 delivers the simultaneous operation signal, the memory element groups 2 and 3 simultaneously initiate the operation and two sequential operations are made with one execution operation. Thus, since a plurality of memory modules perform memory access simultaneously, the information transfer speed between the memory unit and the request unit can be increased.
JP14340177A 1977-11-30 1977-11-30 Control system for memory unit Pending JPS5475941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14340177A JPS5475941A (en) 1977-11-30 1977-11-30 Control system for memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14340177A JPS5475941A (en) 1977-11-30 1977-11-30 Control system for memory unit

Publications (1)

Publication Number Publication Date
JPS5475941A true JPS5475941A (en) 1979-06-18

Family

ID=15337902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14340177A Pending JPS5475941A (en) 1977-11-30 1977-11-30 Control system for memory unit

Country Status (1)

Country Link
JP (1) JPS5475941A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201453A (en) * 1984-03-26 1985-10-11 Fujitsu Ltd Memory access controlling system
JPS618785A (en) * 1984-06-21 1986-01-16 Fujitsu Ltd Access control system for storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60201453A (en) * 1984-03-26 1985-10-11 Fujitsu Ltd Memory access controlling system
JPS618785A (en) * 1984-06-21 1986-01-16 Fujitsu Ltd Access control system for storage device

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