JPS5474714A - Signal distortion improvement circuit - Google Patents

Signal distortion improvement circuit

Info

Publication number
JPS5474714A
JPS5474714A JP14159077A JP14159077A JPS5474714A JP S5474714 A JPS5474714 A JP S5474714A JP 14159077 A JP14159077 A JP 14159077A JP 14159077 A JP14159077 A JP 14159077A JP S5474714 A JPS5474714 A JP S5474714A
Authority
JP
Japan
Prior art keywords
signal
circuit
output signal
delay time
demodulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14159077A
Other languages
Japanese (ja)
Other versions
JPS6044735B2 (en
Inventor
Shinji Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP52141590A priority Critical patent/JPS6044735B2/en
Publication of JPS5474714A publication Critical patent/JPS5474714A/en
Publication of JPS6044735B2 publication Critical patent/JPS6044735B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make possible signal transmission of high fidelity by synthesizing correction signal from the discrimination output signal obtained through level discrimination and compensating the waveform distortion produced in clip processing.
CONSTITUTION: An AND circuit 12 outputs the signal of triangle waveform as the analog AND output signal of the comparison output signal delayed by a specified delay time T2 in a delay circuit 10 and the output signal from a charging-discharging circuit 9. The AND output signal obtainable from the AND circuit 12 is supplied to a signal mixing circuit 7 and is superposed with the demodulation signal having been delayed by a specified delay time T1 in a first delay circuit 6. Namely, a signal mixing circuit 7 is supplied with the demodulation signal with a delay by the specified delay time T1 and the AND output signal of triangle waveform is superposed in the portion shown by a broken line in the figure where the waveform distortion is produced in this demodulation signal, whereby the improvement of signal distortions is accomplished.
COPYRIGHT: (C)1979,JPO&Japio
JP52141590A 1977-11-28 1977-11-28 Signal distortion improvement circuit Expired JPS6044735B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52141590A JPS6044735B2 (en) 1977-11-28 1977-11-28 Signal distortion improvement circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52141590A JPS6044735B2 (en) 1977-11-28 1977-11-28 Signal distortion improvement circuit

Publications (2)

Publication Number Publication Date
JPS5474714A true JPS5474714A (en) 1979-06-15
JPS6044735B2 JPS6044735B2 (en) 1985-10-05

Family

ID=15295539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52141590A Expired JPS6044735B2 (en) 1977-11-28 1977-11-28 Signal distortion improvement circuit

Country Status (1)

Country Link
JP (1) JPS6044735B2 (en)

Also Published As

Publication number Publication date
JPS6044735B2 (en) 1985-10-05

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