JPS5474649A - Stack control mechanism - Google Patents

Stack control mechanism

Info

Publication number
JPS5474649A
JPS5474649A JP14151377A JP14151377A JPS5474649A JP S5474649 A JPS5474649 A JP S5474649A JP 14151377 A JP14151377 A JP 14151377A JP 14151377 A JP14151377 A JP 14151377A JP S5474649 A JPS5474649 A JP S5474649A
Authority
JP
Japan
Prior art keywords
stack
representing
address
area
head address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14151377A
Other languages
Japanese (ja)
Inventor
Yusaku Miki
Hidemi Yamamoto
Yuichi Kimihira
Akio Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14151377A priority Critical patent/JPS5474649A/en
Publication of JPS5474649A publication Critical patent/JPS5474649A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To reduce the overhead of software system and to speed up the operation speed, by constituting the stack control set with the four registers representing the lower limit address of stack area, upper address, head address, and the head address for vacant area.
CONSTITUTION: The stack set 17 constituting the central processing unit is constituted with four registers consisting each of 32-bit, and the data storage state in arbitrary stack area is memorized. That is, the set is constituted with SLA 17 representing the lower limit address at the stack area, SUA 172 representing the upper limit address, stack pointer CSP 173 representing the head address of the control stack, and the data stack pointer DSP 174 representing the head address of the data stack. At this time, the size is taken as SLA<SUA, and the stack area of the main memory unit mmu 4 for the unit is controlled with CSP and DSP.
COPYRIGHT: (C)1979,JPO&Japio
JP14151377A 1977-11-28 1977-11-28 Stack control mechanism Pending JPS5474649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14151377A JPS5474649A (en) 1977-11-28 1977-11-28 Stack control mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14151377A JPS5474649A (en) 1977-11-28 1977-11-28 Stack control mechanism

Publications (1)

Publication Number Publication Date
JPS5474649A true JPS5474649A (en) 1979-06-14

Family

ID=15293702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14151377A Pending JPS5474649A (en) 1977-11-28 1977-11-28 Stack control mechanism

Country Status (1)

Country Link
JP (1) JPS5474649A (en)

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