JPS5467327A - Digital input circuit - Google Patents

Digital input circuit

Info

Publication number
JPS5467327A
JPS5467327A JP13419377A JP13419377A JPS5467327A JP S5467327 A JPS5467327 A JP S5467327A JP 13419377 A JP13419377 A JP 13419377A JP 13419377 A JP13419377 A JP 13419377A JP S5467327 A JPS5467327 A JP S5467327A
Authority
JP
Japan
Prior art keywords
power supply
resistances
switch
acceptance
eliminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13419377A
Other languages
Japanese (ja)
Inventor
Shigeki Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13419377A priority Critical patent/JPS5467327A/en
Publication of JPS5467327A publication Critical patent/JPS5467327A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To prevent malfunction with the acceptance of double keying eliminated by decreasing the voltage drop of a power supply below a threshold level, by closing at least two switch elements at the same time.
CONSTITUTION: From terminals A and B of DC power supply 1, DC voltages are applied to switch 2a and resistance 3a, and the middle point between the both is connected to input terminal C. In the same way, switches 2b, 2c and 2d are connected to switch 2a and resistances 3a in parallel via resistances 3b, 3c and 3d respectively, and respective middle points are connected to input terminals D,E and F. Here, values of resistances 3a...3d are so selected that closing at least two switch elements at the same time decreases the voltage drop of DC power supply 1 below a fixed threshold level. Consequently, the acceptance of double keying is eliminated and its malfuction can be prevented.
COPYRIGHT: (C)1979,JPO&Japio
JP13419377A 1977-11-08 1977-11-08 Digital input circuit Pending JPS5467327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13419377A JPS5467327A (en) 1977-11-08 1977-11-08 Digital input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13419377A JPS5467327A (en) 1977-11-08 1977-11-08 Digital input circuit

Publications (1)

Publication Number Publication Date
JPS5467327A true JPS5467327A (en) 1979-05-30

Family

ID=15122599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13419377A Pending JPS5467327A (en) 1977-11-08 1977-11-08 Digital input circuit

Country Status (1)

Country Link
JP (1) JPS5467327A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61175811A (en) * 1985-01-31 1986-08-07 Toshiba Corp Keyboard device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130138A (en) * 1973-04-11 1974-12-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49130138A (en) * 1973-04-11 1974-12-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61175811A (en) * 1985-01-31 1986-08-07 Toshiba Corp Keyboard device

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